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| austriamicrosystems ag is now ams ag the technical content of this austriamicrosystems datasheet is still valid. contact information: headquarters: ams ag tobelbaderstrasse 30 8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 e - mail: ams_sales @ams.com please visit our website at www.ams.com
as3658 power and audio management unit for portable devices data sheet confidential www.austriamicrosystems.co m revision 1v13 1 - 157 1 general description the as3658 is highly integrated power and audio management unit. the as3658 is designed to include soph isti cated audio features like high performance audio dac and adc. it has several analog and digital audio interface which are explained in detail in the following sections. the as3658 is an integrated solution fo r p ower supply generation and monitoring, battery management including charging. 2 key features system control - serial control interface - on/off control module with boot-rom / gpio - reset generation for system controller - programmable interrupt controller and watchdog - low power off mode (9a; 2.5v ldo on) - 88 bit unique id or boot fuse array - reset with long on-keypress (sw-interuptable) - touchscreen interface (10 bit, interrupt) supply voltage generation - 2 rf programmable low noise ldos (250ma) (1 ld o can be a current controlled switch for hotplug (200ma 40%)) - 1 rf programmable low noise ldo (400ma) - 4 programmable dig. low power ldos(200ma) - 2 general purpose pwm dc/dc step up converter w i th three programmable current sinks (e.g. for - white led); for current mode feedback is automati - cally slected (dcdc_curr1,2,3) - 3 general purpose high efficiency dc/dc step do wn converter (dcdc 1 support dvm) - 1 low noise charge pump with 5v output voltage - 1 ultra low power 2.5v ldo (always on) current sinks - 4 programmable(8-bit) from 0.15ma to 38.25ma (5% ) optional useable as gpios - 3 programmable high voltage (15v) (8-bit) from 0 . 15ma to 38.25ma (5% ) - internal pwm generator (extended time range) (can co ntrol dcdc_curr1,2,3) 10-bit 40s successive approximation adc - two external inputs (adc_in1, adc_in2) battery management - full featured chemistry independent step down ch arger with ga s gauge and current limitation - high current (1.0a) linea r ch arger with external pass transistor (no step down charger) -0.1 battery switch for start-up and trickle charge - integrated usb charger up to 880ma (can be used as w all adapter charger) ; current accuracy 440- 500ma for usb specification, in-circuit trimmable (1.2% trimsteps) - autonomous battery te mperature sup ervision (0oc-45oc or 0oc- 50oc) for 10k and 100k ntc - charging timeout (1h-8h in 30min steps) - charging in stanby mode - completely autonomous (no sw) power management features - wide battery supply range 3.0?5.5v - on-chip bandgap tuning for high accuracy (1%) - thermal and current protection (int. sensor) - standby mode exit by interrupt e.g. onkey/rtc audio - 94db audio dac, 16-48khz sampling rate - two digital audio inputs (2 x i2s interface) - 2.9v low noise ldo for audio dac - two headphone amplifier output with gnd se p aration - two i2s inputs and one i2s output - i2s master mode with programmable sample rate ( c ontrolled by internal pll) - gnd buffer for headphone amplifier - line/ headphone outputs with gnd separation - audio adc, 82db snr with 16ksps - microphone bias supply and amplifier (mono) - 5 band adjustable audio equalizer ( 12db in 3db gain step s) - spdif output - audio mixer and gain stages - pcm interface real time clock (rtc) - alarm and time function - repeated wakeup (every second or minute) - 32khz output - backup battery charger and switchover programmable system clock - 1.6 mhz to 2.3 mhz with 100 khz steps package - bga124 8x8mm, 0.5mm pitch (can be assembled without micro vi a board s) ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 2 - 157 as3658 data sheet confidential - applications 3 applications the as3658 is ideal for pda, pmp, gps-navigation systems and 1 cell li+ or 3 cell nimh powered devices. figure 1. blockdiagram as3658 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 3 - 157 as3658 data sheet confidential - applications figure 2. application diagram as3658 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 4 - 157 as3658 data sheet confidential - applications table of contents 1 general description .............................................................................................................................. 1 2 key features ......................................................................................................................................... 1 3 applications ........................................................................................................................................... 2 4 pin assignments ................................................................................................................................... 6 4.1 pin description ............................................................................................................................................... 7 5 absolute maximum ratings .................................................................................................................. 12 6 electrical characteristics ..................................................................................................................... 13 7 typical operating characteristics ....................................................................................................... 14 8 detailed description-power management functions .......................................................................... 15 8.1 step up dc/dc converters ......................................................................................................................... 15 8.2 current sinks ............................................................................................................................................... 25 8.3 general purpose input / output (curr1_gpio1 ? curr4_gpio4) ....................................................... 30 8.4 backup battery charger .............................................................................................................................. 38 8.5 smooth switchover power management overview ..................................................................................... 41 8.6 battery switch si nt (vsup p ly, battery) ........................................................................................................ 42 8.7 external step down/linear charger ............................................................................................................ 44 8.8 usb charger ............................................................................................................................................... 48 8.9 battery charge controller ............................................................................................................................ 51 8.10 charger supervision functions ................................................................................................................... 63 8.11 step down dc/dc converters ................................................................................................................... 67 8.12 low dropout regulators (ldo) ................................................................................................................. 78 8.13 5v charge pump ....................................................................................................................................... 85 9 detailed description- audio functions ................................................................................................ 87 9.1 audio paths ................................................................................................................................................. 87 9.2 common mode voltage gene ration of hp_cm, line_c m ........................................................................... 89 9.3 audio setup registers ................................................................................................................................. 90 9.4 adc, dac and digital audio input ............................................................................................................... 91 9.5 i2s master mode and pcm mode ............................................................................................................... 95 9.6 line input ..................................................................................................................................................... 98 9.7 five band equalizer .................................................................................................................................... 99 9.8 microphone input ...................................................................................................................................... 105 9.9 audio output mixer .................................................................................................................................... 108 9.10 line output ............................................................................................................................................. 109 9.11 headphone output ................................................................................................................................... 112 9.12 spdif output ........................................................................................................................................... 115 10 detailed description - system functions ........................................................................................ 116 10.1 2c serial interface ................................................................................................................................... 116 10.2 reset generator and xon-key ................................................................................................................ 118 10.3 interrupt controller ................................................................................................................................... 124 10.4 startup ...................................................................................................................................................... 129 10.5 protection functions ............................................................................................................................... . 134 10.6 watchdog ................................................................................................................................................ 135 10.7 general purpose 10 bit adc ................................................................................................................... 136 10.8 internal references (v, i, fclk) .................................................................................................................. 139 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 5 - 157 as3658 data sheet confidential - applications 10.9 real-time clock (rtc) module ............................................................................................................... 140 10.10 touchpen interface ............................................................................................................................... . 143 11 register map ................................................................................................................................... 148 12 package drawings and marking ..................................................................................................... 154 12.1 pinout drawing (top view) ctbga 8x8mm ............................................................................................. 155 13 ordering information ....................................................................................................................... 156 document revision history table 1. revision history chapter rev description of changes date author 1v00 - 23.3.2009 pkm 9.1; 12 1v10 - updated package drawings - updated audio path drawings 15.4.2009 pkm 12,13 1v11 - updated packagemarkings and ordering information 23.9.2009 pkm 12,13 1v12 - updated packagemarkings and ordering information 23.10.2009 pkm 1v13 - typo corrections 23.9.2010 pkm ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 6 - 157 as3658 data sheet confidential - pin assignments 4 pin assignments 1234567891011121314 a nc/ vss _cp lrc lk1 scl k3 vi2s sdo 1 vcp _n vcp _p vcp _ou t vdi g34 _in vdi g1_i n lou t_r line _cm hpl 1 nc/ bv ss b sdi2 sclk1 sdi1 sda vss_c p vcp_i n vdig_ 2 vdig2 _in vdig_ 1 lout_ l hp_c m hpr 2 c q32k sclk2 hpr1 hpl2 d dcdc _sens e_p1 mclk 2 sdo3 scl vdig_ 4 vdig_ 3 mclk 1 lrclk 2 alvd d hp_ cm_ pwr e vsup ply_4 dcdc _sens e_n1 lrclk 3 bvss avdd linr f vsup ply_3 dcdc _gate 1 spdif xres et xint mics vdac linl g lx3 dcdc _gate 2 dcdc _sens e_n2 dcdc _sens e_p2 vssa micn vsup ply_6 vsu p_s w12 h pgnd 3 pgnd 2 dcdc _fb1 fb3 vssa micp vbat_ sw12 vsu p_s w12 j lx2 vss_c h dcdc _fb2 fb2 vssa vref bat_s w vbat _sw 12 k vsup ply_1 vsup ply_2 fb1 agnd isens n isen sp l lx1 voff_ b curr 4_gpi o4 dcdc _cur r1 dcdc _cur r3 gnd_ sw rpro gram cref gnd_ sens e rbia s m pgnd 1 vgat e v_bat vba ck n pgat e1 vsup ply_5 xon curr 1_gpi o1 curr 3_gpi o3 dcdc _cur r2 adc_i n1 adc_i n2 vrf_2 vcha rger v2_5 xou t32 p nc/ vssa ch_s ense_ p ch_s ense_ n vcur r_gpi o vss_c urr curr 2_gpi o2 vsup_ usb v_usb vrf1_ in vrf_1 vrf23 _in vrf_3 xin32 nc/ vss a ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 7 - 157 as3658 data sheet confidential - pin assignments 4.1 pin description table 2. pin list ctbga124, 8x8mm ( as3658 ) pin name pin number pin type supply description charger v_usb p 8 p usb voltage supply input vsup_usb p7 p supply output of usb charger (connect to vsupply) vcharger n11 p high voltage input coming from the charger; if the charger is used connect a ceramic capacitor of 1f vgate m2 a switch on control pin for the ex ternal pmos fet transistor of the charger step down converter voff_b l2 a switch off control pin for the external pmos fet transistor of the charger step down buck converter vss_ch j2 p ground pad of step down charger vbat_sw12 h13 p v bat battery switch inpu t1 (battery side) vbat_sw12 j14 p v bat battery switch inpu t2 (battery side) vsup_sw12 g14 p v supply battery switch input1 (supply side) vsup_sw12 h14 p v supply battery switch input2 (supply side) bat_sw j13 a battery switch output for external pmos ch_sense_n p3 a v supply charger step down converter, external shunt resistor negative connection ch_sense_p p2 a v supply charger step down converter, ex ternal shunt resistor positive connection isensp k14 a v2_5 positive sensing input voltage for the external charging current shunt resistor isensn k13 a v2_5 negative sensing input voltage for the external charging current shunt resistor serial interface scl d6 di v supply scl input in i 2 c mode sda b5 dio v supply sda input / output in i 2 c mode control interfaces xreset f7 od v supply bidirectional reset pin ? add an external pull-up resistor to the digital supply xint f8 od v supply interrupt pin - add an external pull-up resistor to the digital supply xon n4 ipu v2_5 input pin to startup the system (power on), in ternal pull-up, apply zenerzap-programming voltage here rtc q32k c1 od v supply 32khz oscillator digital output xin32 p13 a v2_5 32khz crystal oscillator input xout32 n14 a v2_5 32khz crystal oscillator output ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 8 - 157 as3658 data sheet confidential - pin assignments internal refs vsupply_5 n3 p supply for voltage measurement, always connect to vsupply v_bat m13 p v bat battery supply for reference blocks. rprogram l9 a v2_5 select register setup at startup. v2_5 n12 p internal regulator analogue output cref l10 a v2_5 reference voltage bypass capacitor connection rbias l14 a v2_5 internal bias reference resistor (connect 220k resistor) gnd_sense l13 p vssa gnd reference for analog bl ocks (connect to gnd plane separate) adc_in1 n8 a v2_5 analog input1 for adc10 adc_in2 n9 a v2_5 analog input2 for adc10 vback m14 a backup battery connection current sinks curr1_gpio1 n5 a v curr_ gpio current sink 1, or gpio1 curr2_gpio2 p6 a v curr_ gpio current sink 2, or gpio2 curr3_gpio3 n6 a v curr_ gpio current sink 3, or gpio3 curr4_gpio4 l5 a v curr_ gpio current sink 4, or gpio4 dcdc_curr1 l6 a v curr_ gpio step up dc/dc converter2 current source 1 dcdc_curr2 n7 a v curr_ gpio step up dc/dc converter2 current source 2 dcdc_curr3 l7 a v curr_ gpio step up dc/dc converter2 current source 3 vcurr_gpio p4 a supply voltage of gpios and current sinks vss_curr_gpio p5 a v curr_ gpio ground pad of current sink / gpio pads general purpose dc/dc step up converter 1 and 2 vsupply_4 e1 p supply for dcdc step up and co ntrol interface, always connect to vsupply dcdc_fb1 h4 a v supply step up dc/dc converter1 feedback input dcdc_gate1 f2 a v supply step up dc/dc converter1 control for external mosfet dcdc_sense_p1 d1 a v supply step up dc/dc converter1 external shunt resistor positive connection dcdc_sense_p2 g6 a v supply step up dc/dc converter2 external shunt resistor positive connection dcdc_sense_n1 e2 a v supply step up dc/dc converter1 external shunt resistor negative connection dcdc_sense_n2 g4 a v supply step up dc/dc converter2 external shunt resistor negative connection table 2. pin list ctbga124, 8x8mm ( as3658 ) pin name pin number pin type supply description ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 9 - 157 as3658 data sheet confidential - pin assignments dcdc_gate2 g2 a v supply step up dc/dc converter2 control for external mosfet dcdc_fb2 j4 a v supply step up dc/dc converter2 feedback input linear regulators (ldos) vrf1_in p9 p v supply supply pad for rf1 ldo (vrf_1), always connect to supply>3.0v vrf_1 p10 a v rf1_in output voltage of one of the rf ldo?s; can be used as high- side switch, if used as ldo connect a ceramic capacitor of 1f (20%) or 2.2f (+100%/-50%) vrf23_in p11 p v supply supply pad for rf2 and rf3 ldo (vrf_2, vrf_3), always connect to supply>3.0v vrf_2 n10 a v rf23_in output voltage of one of the rf ldo?s; can be used as high- side switch, if used as ldo connect a ceramic capacitor of 1f (20%) or 2.2f (+100%/-50%) vrf_3 p12 a v rf23_in output voltage of one of the rf ldo?s; can be used as high- side switch, if used as ldo connect a ceramic capacitor of 1f (20%) or 2.2f (+100%/-50%) vdig1_in a10 p v supply supply pad for dig1 ldo (vdig_1) vdig_1 b10 a v dig1_in output voltage of one of the dig ldo?s. connect a ceramic capacitor of 1f (20%) or 2.2f (+100%/-50%) vdig2_in b9 p v supply supply pad for dig2 ldo (vdig_2) vdig_2 b8 a v dig2_in output voltage of one of the dig ldo?s. connect a ceramic capacitor of 1f (20%) or 2.2f (+100%/-50%) vdig34_in a9 p v supply supply pad for dig3 and dig4 ldo (vdig_3, vdig_4) vdig_3 d8 a v dig3_in output voltage of one of the dig ldo?s. connect a ceramic capacitor of 1f (20%) or 2.2f (+100%/-50%) vdig_4 d7 a v dig4_in output voltage of one of the dig ldo?s. connect a ceramic capacitor of 1f (20%) or 2.2f (+100%/-50%) charge pump vcp_in b7 p v supply supply pad for charge pump, always connect to supply>3.0v vcp_n a6 a v supply hvs charge pump flying capacitor positive side vcp_p a7 a hvs charge pump flying capacitor negative side vcp_out a8 a charge pump output, connect a ceramic capacitor of 2.2f (+100%/-50%) vss_cp b6 a v supply ground pad of charge pump dcdc step down converters pgate1 n1 a v supply gate output for external pm os.(dcdc step down controller 1) vsupply_1 k1 p supply pad for dcdc_step down converter1, always connect to vsupply lx1 l1 a v supply dc/dc step down converter1 output fb1 k4 a v supply dc/dc step down converter1 feedback pgnd1 m1 a v supply power ground of dcdc step down converter1 table 2. pin list ctbga124, 8x8mm ( as3658 ) pin name pin number pin type supply description ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 10 - 157 as3658 data sheet confidential - pin assignments vsupply_2 k2 p supply pad for dcdc_step down converter2, always connect to vsupply lx2 j1 a v supply dc/dc step down converter2 output fb2 j7 a v supply dc/dc step down converter2 feedback pgnd2 h2 a v supply power ground of dcdc step down converter2 vsupply_3 f1 p supply pad for dcdc_step down converter3, always connect to vsupply lx3 g1 a v supply dc/dc step down converter3 output fb3 h6 a v supply dc/dc step down converter3 feedback pgnd3 h1 a v supply power ground of dcdc step down converter3 audio vsupply_6 g13 p supply for vi2s regulator vi2s a4 p supply pad for i2s interface, connect to vdac supply sdi1 b4 i vi2s i2s_1 data input to dac sdo1 a5 o vi2s i2s_1 data output from adc sclk1 b3 i/o vi2s i2s_1 shift clock input or output lrclk1 a2 i/o vi2s i2s_1 left/right clock input or output mclk1 d9 i/o vi2s master clock input or output for i2s1: dac (128*fsdac or 256 *fsdac) sdi2 b1 i vi2s i2s_2 data input to dac sclk2 c2 i vi2s i2s_2 shift clock lrclk2 d10 i vi2s i2s_2 left/right clock mclk2 d2 i vi2s master clock input for i2s2: dac (128*fsdac or 256 *fsdac) sdo3(x-) d5 i/o vi2s i2s_3 data output (if touchpen interface disabled) touchpen interface x- input/output (if touchpen interface enabled) sclk3(x+) a3 i/o vi2s i2s_3 shift clock output (if touchpen interface disabled) touchpen interface x+ input/ou tput (if touchpen interface enabled) lrclk3(y-) e4 i/o vi2s i2s_3 left/right clock output (i f touchpen interface disabled) touchpen interface y- input/ou tput (if touchpen interface enabled) spdif(y+) f4 i/o vi2s spdif digital output (if touchpen interface disabled) touchpen interface y+ input/ou tput (if touchpen interface enabled) agnd k11 a vdac cm voltage bypass capacitor connection (1.45v) vref j11 a vdac vdac voltage bypass capacitor connection (2.9v) linl f14 a vdac line input left channel. linr e14 a vdac line input right channel gnd_sw l8 o v supply digital output for controlling the external nmos table 2. pin list ctbga124, 8x8mm ( as3658 ) pin name pin number pin type supply description ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 11 - 157 as3658 data sheet confidential - pin assignments note: the following are the pin types i : digital input pin ipd : digital input pin with internal pull-down resistor ipu : digital input pin with internal pull-up resistor iodpu : digital input / open drain output pin with internal pull-up resistor o : digital output pin od : digital open drain output pin; requires external pull-up resistor io : digital input / output pin a : analog pin p: power pin vdac f13 a vdac 2.9v output voltage of one of dac ldo; connect a ceramic capacitor of 1f (20%) or 2.2f (+100%/-50%) hp_cm b12 a avdd bypass capacitor connection of common mode voltage of audio headphone amplifier (avdd/2) hp_cm_pwr d14 a avdd buffered voltage of hp_cm line_cm a12 a alvdd bypass capacitor connection of common mode voltage of audio line out amplifier (alvdd/2) lout_l b11 a alvdd line out output left channel lout_r a11 a alvdd line out output right channel alvdd d13 p supply pad of line out amplifier avdd e13 p supply pad of headphone amplifier hpl1 a13 a avdd headphone output1 left channel hpr1 c13 a avdd headphone output1 right channel hpl2 c14 a avdd headphone output2 left channel hpr2 b14 a avdd headphone output2 right channel micn g11 a vdac microphone input n micp h11 a vdac microphone input p mics f11 a v supply microphone supply (2.95v) / remote input vss bvss e11 p avdd power ground of headphone amplifier vssa g9 vss analog ground pad vssa h9 vss analog ground pad vssa j8 vss analog ground pad nc/vss_cp a1 vss analog ground pad nc/vssa p1 vss analog ground pad nc/vssa p14 vss analog ground pad nc/bvss a14 vss power ground of headphone amplifier table 2. pin list ctbga124, 8x8mm ( as3658 ) pin name pin number pin type supply description ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 12 - 157 as3658 data sheet confidential - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 3 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or an y othe r cond itions beyond those indicated in section 6 electrical characteristics on page 13 is not implied. exposure to absolute maxi mum ratin g conditions for extended periods may affect device reliability. table 3. absolute maximum ratings parameter min max unit note high voltage pins (v in_hv) -0.3 17.0 v applicable for high voltage pins 1 1. hv pins vcharger, vgate, voff_b, dcdc_curr1, dcdc_curr2, dcdc_curr3 5v pins (v in_mv) -0.3 7.0 v applicable for pins 5v-pins 2 2. 5v pins are v_usb, ch_sense_n, ch_sense_p, vsup_sw1, vsup_sw2, vbat_sw 1, vbat_sw2, v_bat, scl, sda, xreset, xint, vsupply_3, curr1_gpi o1?curr4_gpio4, dcdc_gate1, dcdc_gate2, dcdc_sense_p1, dcdcsense_p2, dcdc_sense_n1, dcdc_sense_n2, dcdc_fb1, dcdc_fb2, vcl, vcp_out, vcp_ n, vcp_p, vcp_in, vcp_in, vrf1, vref 1_in, vrf2, vrf23_in, vrf3, vdig1, vdig1_in, vdig2, vdig2_in, vdig 34_in, vdig_3, vdig_4, pgate1 vsupply_1, vsupply_2, lx1, lx2, gnd_sw, vsupply_4, line_cm, hp _cm_pwr, hp_cm, hplx, hprx, alvdd, avdd, lsp_r, bvss, lsp_l, avdd, vsupply_5, vsupply_6 3.3v pins (v in_lv) -0.3 5.0 v applicable for 3.3v-pins 3 3. 3.3v pins are isensep, isensen, adc_inx, rprogram, v2_5, cre f, on, vi2s, sdix, sclkx, mclkx, lrclkx, sdox, spdif, agnd, vref, linl,linr, vdac, q 32k, xin32, xout32, vbac k, mics, micn, micp input pin current (i in) -25 +25 ma at 25 oc, norm: jedec 78 storage temperature range (t strg) -55 125 oc humidity 5 85 % noncondens electrostatic discharge 1kv (v esd) -1000 1000 v norm: mil 883 e method 3015; setup 4 applicable for pins: all 4. the following pins are connected to esd setup: vsupply_1...vsupply_6, vcp_ in, vrf1_in, vrf2_in, vcurr connected together vdig1_in, vdig2_in, vdig34_in connected together avdd, alvdd connected together vbat_sw1 and vbat_sw2 connected together vsup_sw1 and vsup_sw2 connected together all vss connected together total power dissipation 1w t a = 70oc 0.72 w t a = 84oc package body temperature 260 c ipc/jedec j-std-020c, reflects moisture sensitivity level only the lead finish for pb-free leaded packages is matte tin (100% sn). solder profile 5 5. austriamicrosystems strongly recommends to use underfill. 235 245 c t peak 30 45 s d well , above 217 c moisture sensitive level 3 1 represents a max. floor live time of 168h ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 13 - 157 as3658 data sheet confidential - electrical characteristics 6 electrical characteristics table 4. electrical characteristics symbol parameter condition min typ max units operating conditions v hv high voltage vcharger, vgate, dcdc_curr1,dcdc_curr2, dcdc_curr3 0.0 15.0 v v bat , v supply, vcurr_gpio battery, supply voltage for pins v_bat, vsupply1-6 (always connect all vsupply1-6 pins together), vsup_sw1-2, vbat_sw1-2, vrf1 _in, vrf2_in, vcp_in, avdd, alvdd 3.0 3.6 5.5 v v2_5 voltage on pin v2_5 internally generated 2.4 2.5 2.6 v vcp_out output voltage charge pump volta ge generated by charge pump 4.9 5.2 5.6 v t amb ambient temperature -40 25 85 oc i lowpower low power mode current consumption current consumption in low power mode with step down charger on 1 1. with register bit low_power_on = 1, only rf1=3.3v ,vout2=1.2v, battery 3.6v,vcharger=6.0v, no additional external loads 7m a with step down charger off 2 2. with register bit low_power_on = 0, all regulators switched off, no additional external loads 280 a i poweroff power off mode current consumption current consumption in power off mode 3 3. after setting register bit xon_enable=1 and power_off=1; only v2_5 is active in power off mode 4. during startup from the ac/dc adapt er, the battery voltage can be below 3.0v 10 a ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 14 - 157 as3658 data sheet confidential - typical operating characteristics 7 typical operating characteristics see individual block description ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 15 - 157 as3658 data sheet confidential - detailed description-power management functions 8 detailed description-power management functions the power management function consist of the dcdc step up converters, current sink, gpios, general purpose 10 bit adc, backup battery charger, main battery charger and power path management (consisting of the battery switch, external step down/linear charger, usb charger and batt ery charge controller), step down dc/dc converters, low dropout regulators (ldos) and 5v charge pump. 8.1 step up dc/dc converters figure 3. dc/dc step-up converter 1 ! !" #$ %& ''(%& !)( ! * + ,! , + )( !)( " " "," ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 16 - 157 as3658 data sheet confidential - detailed description-power management functions figure 4. dc/dc step-up converter 2 table 5. dc/dc converter parameters symbol parameter min typ max unit note i vdd quiescent current 140 a pulse skipping mode v fb1 feedback voltage for external resistor divider: 1.20 1.25 1.30 v for constant voltage control v fb2 feedback voltage for current sink regulation 0.5 v dcdc_curr1, dcdc_curr2 or dcdc_curr3 i dcdc_fb additional tuning current at dcdc_fb 031a adjustable by software in 1a steps accuracy of feedback current -5 5 % @ full scale v rsense_max current limit voltage at rsense 100 mv e.g.: 0.65a for 0.15 sense resistor r sw switch resistance 1 on-resistance of external switching transistor i load load current 0 50 ma at 15v output voltage f in switching frequency f clk_int / 2 mhz internal clk frequency/2 programmable: 0.8 to 1.15 mhz ! " ##$ ##% #&' # () *%+ , $ %$ #&- ). . / %$ %$$%/+ "% &0'/ 1 22!3 #&'% 4 %$ %%% # %% %$ %% #/# ##/$ ##% ! 005/67 7 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 17 - 157 as3658 data sheet confidential - detailed description-power management functions the dc/dc step up converter is a high efficiency current mode pwm regulator, which provides an output voltage dependent on the maximum vds voltage of the external tr ansistor, and maximum load current selectable by the external shunt resistor. for example: 5v,500ma @ 1.1mhz 25v,50ma @ 1.1mhz 40v,20ma @ 550khz a constant switching frequency results in a low noise on supply and output voltage. 8.1.1 feedback selection for step up dcdc 1, the feedback is always dcdc_fb1. for step up dcdc 2 following feedback selections are possible: stpup2_fb selects the type of feedback for the dcdc_step_up2 converter: dcdc_curr1, dcdc_curr2, dcdc_curr3 or dcdc_fb2 feedback (see f igure 5) setting stpup2_fb to 00b enables the feedback on dcdc_fb2, stpu p2_fb to 01b enables feedback at pin dcdc_curr1, setting step_up_fb to 10b enables feedback at pin dcdc_curr2 and setting step_up_fb to 11b enables feedback at pin dcdc_curr3. the step-up converter is regulated such that the required current at the feedback path can be supported. always choose the path with the higher voltage drop as feed back to guarantee adequate supply for the other, unregulated path. to protect the dcdc output voltage against overvol t age, if a led string is brok en, set stpup2_prot=1. in this mode the output voltage will be limited by limiting the dcdc_fb voltag e to 1.25v (select the external resistor network to adjust this limitation voltage). c out output capacitor 2.2 f ceramic, 20% l inductor 10 h use inductors with small c parasitic (<100pf) to get high efficiency t min_on minimum on time 130 ns mdc maximum duty cycle 91 % table 5. dc/dc converter parameters symbol parameter min typ max unit note ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 18 - 157 as3658 data sheet confidential - detailed description-power management functions figure 5. dc/dc step up 2 converter with regulation of led string on pin dcdc_curr1,2 or 3 ,"8 8 ! " # $% &' $ ()*+), -./) (00( 12 ! ## 3 !+)" )(/ &456 ! ! )0 +0 7 ! )0 0 )0 8- (50 #9 : %() 7) !7 +) )0 8)* " " 7 + 7 7(:) 6+5( 8)),-(")) ; <<==&> )0 8- (+ ,, +? @ '! 4! 7)/50 )( 7)/ 0+) "0 0+0 " 7 0+0 +))) <<& ! ## 3 0(.)*+), 8 <<&( ) )),! ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 19 - 157 as3658 data sheet confidential - detailed description-power management functions figure 6. dc/dc step up 1 converter with regulated output voltage of 5v. feedback is at pin dcdc_fb1 voltage feedback: (see figure 6) for step up dcdc 1 voltage feedback is always selected on pin dcdc_fb1. for step-up up dcdc 2 set step2_fb to 00 to ena ble voltage feedback at pin dcdc_fb2. bit stepx_res (x = 1 or 2) should be set to 1 in voltage feedback mode using two resistors. the output voltage is regulated to a constant value, given by: 1 2 21 _ _ 25.1 ri r rr v fb dcdc i outstepup ?+ + = if r2 is not used, the output voltage is: v stepup_out : step up regulator output voltage r 1 feedback resistor r1 r 2 feedback resistor r2 i vturning : tuning current on dcdc_fb pin: stpupx_v (0a to 15a (1a steps)) (x= 1 or 2) !" #$ % && ' %() && & #* +,, - #). ( #( (# #( (# # / " 0,#+, #1 23, 4% 5 ! )2 0 10 1#!+ 0 " 0, # 06 % 7 ' 7 ! ' 1#!+ 10 "8 !3, 0 2 10 "8 ,+ "0#"' , " ,+, #! '# 1 " ,+, # + 0 "0 "0 1 _ _ 25.1 ri v fb dcdc i outstepup ?+= ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 20 - 157 as3658 data sheet confidential - detailed description-power management functions example: table 6. step up output voltage (voltage mode or protection voltage) i vtuning v stepup_out v stepup_out a r1=1m ,r2 not used r1=500k ,r2=64k note: the voltage on pin dcdc_curr1, dcdc_curr2 and dcdc_curr3 must never exceed 15v 0-1 1 1-1 1 . 5 2-1 2 3 - 12.5 4- 1 3 5 6.25 13.5 67 . 2 51 4 7 8.25 14.5 89 . 2 51 5 9 10.25 15.5 10 11.25 16 11 12.25 16.5 12 13.25 17 13 14.25 17.5 14 15.25 18 15 16.25 18.5 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 21 - 157 as3658 data sheet confidential - detailed description-power management functions figure 7. dc/dc step up converter 1 wit h regulated output voltage (15v), and switch off function of output voltage, to reduce shutdown current as the output voltage is always on, an additional output transistor can be added to reduce shutdown current through r1, r2 and the connected output circuit. note: a similar circuit can be used for step up converter 2. 8.1.2 stepup1 load detection a nd overcurrent protection circuit this circuit protects the dcdc step up1 converter during shor t circuit and startup, by regu lation of the output current. an additional feature is the detection of a minimum output load o f the step-up converter. it is also possible to use this circuit without the dcdc step up converte r, by using the sense resistor only: detection circuit: if the voltage on r sense exceeds v detect for more than 1msecond, or the dcdc step up converter is not in pulseskip for more than 1 millisecond, the stepup1_det bit will be set. overcurrent protection: if the overcurrent voltage v ovcurrent has been exceeded by more than 5 msec the bit stpup1_oc will be set and can only reset, by switching off and on the protection circui t by writing stpup1_shortprot 0 ? 1. if stepup1_oc is set the load will be disconnected, if stpup1_oc_timeout=1 table 7. stepup1 protection/detection circuit parameters symbol parameter min typ max unit note v detect detection threshold 2 12.5 25 mv for rsense=0.150 => 83ma typ. v ovcurrent overcurrent threshold rising 150 180 215 mv for rsense=0.150 => 1.2a typ. v ovhysteresis overcurrent hysteresis 50 mv t ov_timeout overcurrent timeout 5 ms interrupt and/or external pmos switching off after timeout f clk_int = 2.2mhz t detect detection denounce time 1ms f clk_int = 2.2mhz !" # $ % &% '()* # # + !, # $ -.. $ ''/ $ ''/ "## 0& !*1) !))!' !))! !#0 $ 2.!-.!3 45. '6( 7 *4 2 32 $3! - 2 2.! 28 (9 %9 % 3! - $ 32 : 5. 2 4 32 : .- 2! %. .-.! %! 3 .-.! - 2 2 2 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 22 - 157 as3658 data sheet confidential - detailed description-power management functions figure 8. stepup 1 load detection and ov ercurrent protection application circuit !""#$%&'$(( !"# ) * + ,"+ &-%)%.% /.0 /.0 $(%%1.2+ %$%& )) # $30 .+ $ # $30 .+ $ %$ %$ 0 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 23 - 157 as3658 data sheet confidential - detailed description-power management functions 8.1.3 step up dcdc converter registers table 8. step up dc/dc bit definitions addr: 30 step up dc/dc control this register controls the different modes of the step up dcdc converter bit bit name default access description table 9. step up dc/dc bit definitions addr: 32 step up dc/dc control this register controls the different modes of the step up dcdc converter bit bit name default access description 5 stpup1_on rom r/w on/off control of the step up dc/dc converter1 6 stpup2_on rom r/w on/off control of the step up dc/dc converter2 0 stpup2_clkinv 00h r/w invert i nput clock of step up2 converter 0 use positive edge of internal clk 1 use negative edge of internal clk 1 stpup1_freq 00h r/w defines the clock frequency of the step up1 dc/dc converter; 0f clk_int /2 (0.8 to 1.15 mhz) 1f clk_int /4 (0.4 to 0.575 mhz) 2 - 00h n/a always set to 0 3 stpup1_res 00h r/w gain selection for dcdc step_up1: 0 select 0 if dcdc is used with current feedback (dcdc_curr1,dcdc_curr2,dcdc_curr3) or if dcdc_fb is used with current feedback only (only r1,c1 connected; (see figure 6) ) 1 select 1 if dcdc_fb1 or dcdc_fb2 is used with external resistor divider (2 resistors) 4 stpup2_fb_auto 00h rw 0 step_up_fb select the feedback of the dcdc converter 1 the feedback is automatically chosen within the current sinks dcdc_curr1,dcdc_ curr2 and dcdc_curr3 (never dcdc_fb). only those are used for this selection, which are enabled and connected to the step up converter (currx_ctrl must be 10) 5 stpup2_freq 00h r/w defines the clock frequency of the step up2 dc/dc converter 0 f clk_int /2 (0.8 to 1.15 mhz) 1 f clk_int /4 (0.4 to 0.575 mhz) 6 - 00h n/a always set to 0 7 stpup2_res 00h r/w gain selection for dcdc step_up2: 0 select 0 if dcdc is used with current feedback (dcdc_curr1,dcdc_curr2,dcdc_curr3) or if dcdc_fb is used with current feedback only (only r1,c1 connected; (see figure 6) ) 1 select 1 if dcdc_fb1 or dcdc_fb2 is used with external resistor divider (2 resistors) ams ag technical content still valid table 10. step up dc/dc bit definitions addr: 33 step up1 dc/dc control this register controls the diff erent modes of the step up1 dcdc converter bit bit name default access description www.austriamicrosystems.co m revision 1v13 24 - 157 as3658 data sheet confidential - detailed description-power management functions 4:0 stpup1_v 00h r/w defines the tuning current at dcdc_fb1 pin; 00000 0 a 00001 1 a ..... 11111 31 a 5 stpup1_clkinv 00h r/w invert input clock of step up1 converter; 0 use positive edge of internal clk 1 use negative edge of internal clk 6 stpup1_shortprot 00h rw enables protection and detection circuit for dcdc step up1 0 no protection and load detection 1 short protection and load detection enabled 7 stpup1_oc_timeout 00h rw controls gpio1 switch off, af ter overcurrent timeout (5ms) for dcdc step up1 0 disabled 1 enabled table 11. step up dc/dc bit definitions addr: 34 step up2 dc/dc control this register controls the diffe rent modes of the step up2 dcdc converter bit bit name default access description 4:0 stpup2_v 00h r/w defin e s the tuning current at dcdc_fb2 pin; 00000 0 a 00001 1 a ..... 11111 31 a 6:5 stpup2_fb 00h r/w controls the feedback source 00 dcdc_fb enabled (external resistor divider) 01 dcdc_curr1 feedback enabled (feedback through white leds) 10 dcdc_curr2 feedback enabled (feedback through white leds) 11 dcdc_curr3 feedback enabled (feedback through white leds) ams ag technical content still valid table 12. stpup1_det and stpup1_oc bit definitions addr: 53 low voltage status bit definitions this register shows the status of the overcurrent protection of the stepup1dcdc bit bit name default access description www.austriamicrosystems.co m revision 1v13 25 - 157 as3658 data sheet confidential - detailed description-power management functions 8.2 current sinks these are general-purpose current sinks intended to contro l the backlight(s), buzzer and vibrator. the low voltage current sink has an integrated protection against over voltage and can therefore also drive inductive loads (v protect ). dcdc_curr1 and dcdc_curr2, dcdc_curr3 are high voltage ( 15v) current sinks, e.g. fo r series of white leds curr1_gpio, curr2_gpio, curr3_gpio, c urr4_ g pio are four 5v, 38.25ma cu rrent sinks, e.g. for buzzer, vibrator, leds curr1_gpio, curr2_gpio, curr3_gpio, curr4_gpio can be u s ed as general propose input/output (gpio) functions optional (described in section general purpose input / output (curr1_gpio1 ? curr4_gpio4) ). 7 stpup2_prot 00h rw dcdc conve r ter 2 overvoltage protection to prevent damage of external nfet, if dcdc_curr1 or dcdc_curr2 or dcdc_curr3 feedback selected, and no led string connected: 0 overvoltage protection disabled 1 switch off dcdc step up 2 if the voltage on dcdc_fb2 exceeds 1.25v 6 stpup1_oc na r step up overcurrent status bit 0 v rsense < v ovcurrent 1 v rsense > v ovcurrent for more than 5 msec (latched state) 7 stpup1_det na r step up detection status register 0 v rsense < v detect for more than 1msecond, and dcdc step up converter is in pulseskip for more than 1 millisecond 1 v rsense > v detect for more than 1msecond, or the dcdc step up converter is not in pulseskip for more than 1 millisecond table 11. step up dc/dc bit definitions addr: 34 step up2 dc/dc control this register controls the diffe rent modes of the step up2 dcdc converter bit bit name default access description ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 26 - 157 as3658 data sheet confidential - detailed description-power management functions 8.2.1 high voltage current sink s (dcdc_curr1, dcdc_curr2 and dcdc_curr3) current sinks dcdc_curr3, dcdc_curr1 and dcdc_curr2 can be controlled individually. the step-up dcdc converter may supply them with voltages up to 15v. if any of these current sinks is used, connected vcurr_gpio to a supply with at least 3.0v table 13. current sinks characteristics symbol parameter min typ max unit note . table 14. dcdc_curr1 current sink current bit definition addr: 39 dcdc_curr1 value this register controls the current value of the dcdc_curr1 current sink bit bit name default access description table 15. dcdc_curr2 current sink current bit definition addr: 40 dcdc_curr2 value this register controls the current value of the dcdc_curr2 current sink bit bit name default access description i dcdc_curr1,2,3 dcdc_curr1,2 and dcdc_curr3 current, 00h-3fh 0 38.25 ma for v(dcdc_currx) > 0.45v resolution = 0.15ma i dcdc_protect current sink protection current 2 a protection current if stpup2_on=1 and dcdc_currx_current=00h absolute accuracy -5 +5 % all current sinks v dcdc_curr1 , v dcdc_curr2, v dcdc_curr3 voltage compliance 0.45 15 v during normal operation 7:0 dcdc_curr1_current 00h r/w de fines the current into dcdc_curr1 if enabled by dcdc_curr1_ctrl 00h power down (default state) 01h 0.15ma (lsb) .... ffh 38.25ma 7:0 dcdc_curr2_current 00h r/w d e fines the current into dcdc_curr2 if enabled by dcdc_curr2_ctrl 00h power down (default state) 01h 0.15ma (lsb) .... ffh 38.25ma ams ag technical content still valid table 16. dcdc_curr3 current sink current bit definition addr: 45 dcdc_curr3 value this register controls the current value of the dcdc_curr3 current sink bit bit name default access description table 17. current sink control bit definition addr: 58 curr control this register controls the mode of the dcdc current sinks bit bit name default access description www.austriamicrosystems.co m revision 1v13 27 - 157 as3658 data sheet confidential - detailed description-power management functions 7:0 dcdc_curr3_current 00h r/w defines the current into dcdc_curr3 if enabled by dcdc_curr3_ctrl 00h power down (default state) 01h 0.15ma (lsb) .... ffh 38.25ma 1:0 dcdc_curr1_ctrl 00b r/w on/of f control of the pad dcdc_curr1 00 current sink is turned off 01 current sink is active 10 current sink is active and led string connected to stpup2. required for automatic feedback selection 11 controlled by pwm generator (do not set pwm_div) 3:2 dcdc_curr2_ctrl 00b r/w on/off control of the pad dcdc_curr2 00 current sink is turned off 01 current sink is active 10 current sink is active and led string connected to stpup2. required for automatic feedback selection 11 controlled by pwm generator (do not set pwm_div) 5:4 dcdc_curr3_ctrl 00b r/w on/off control of the pad dcdc_curr3 00 current sink is turned off 01 current sink is active 10 current sink is active and led string connected to stpup2. required for automatic feedback selection 11 controlled by pwm generator (do not set pwm_div) ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 28 - 157 as3658 data sheet confidential - detailed description-power management functions 8.2.2 low voltage current sink (curr1_gpio1 ? curr4_gpio4) curr1_gpio1 ? curr4_gpio4 can be controlled individual ly. each one can sink up to 38.25ma. the voltage on the current sinks must not exceed the supply vcurr_gpio (can be connected e.g. to v supply ). the low voltage current sinks and the gpio pins share the same pins (see gene ral purpose input / output (curr1_gpio1 ? curr4_gpio4) on page 30) for enabling/disabling of the current sinks / gpio functions. table 18. current sinks characteristics symbol parameter min typ max unit note table 19. curr1 current sink current bit definition addr: 41 curr1 control this register controls the mode of the curr1 current sinks bit bit name default access description table 20. curr2 current sink current bit definition addr: 42 curr2 control this register controls the mode of the curr2 current sinks bit bit name default access description i curr1,2,3,4 curr1_gpio1.... curr4_gpio4 current, 00h-1fh 0 38.25 ma for v(currx_gpiox) > 0.2v resolution = 0.15ma, each current sink absolute accuracy -5 +5 % all current sinks v curr1,2,3,4 voltage compliance 0.2 v(vcu rr) v during normal operation 7:0 curr1_current (00)h r/w de fi nes the current into curr1_gpio1 if gpio1_mode = 011b and output enabled (e.g. gpio1=1) 00h power down (default state) 01h 0.15ma (lsb) .... ffh 38.25ma 7:0 curr2_current (00)h r/w define s the current into curr2_gpio2 if gpio2_mode = 011b and output enabled (e.g. gpio2=1) 00h power down (default state) 01h 0.15ma (lsb) .... ffh 38.25ma ams ag technical content still valid table 21. curr3 current sink current bit definition addr: 43 curr3 control this register controls the mode of the curr3 current sinks bit bit name default access description table 22. curr4 current sink current bit definition addr: 44 curr4 control this register controls the mode of the curr4 current sinks bit bit name default access description www.austriamicrosystems.co m revision 1v13 29 - 157 as3658 data sheet confidential - detailed description-power management functions 7:0 curr3_current (00)h r/w defines the current into curr3_gpio3 if gpio3_mode = 011b and output enabled (e.g. gpio3=1) 00h power down (default state) 01h 0.15ma (lsb) .... ffh 38.25ma 7:0 curr4_current (00)h r/w defin e s the current into curr4_gpio3 if gpio4_mode = 011b and output enabled (e.g. gpio4=1) 00h power down (default state) 01h 0.15ma (lsb) .... ffh 38.25ma ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 30 - 157 as3658 data sheet confidential - detailed description-power management functions 8.3 general purpose i nput / output (curr1_g pio1 ? curr4_gpio4) figure 9. curr1_gpio1 ? curr4_gpio4 block diagram the device contains 4 high current gpio pins, which share the same pins as the low voltage current sinks and are cap able of sinking 100ma from vcurr_gpio voltage. each of the pins can be configured as open drain nmos or push-pull output with vcurr_gpio high levels, as high impedance output or as digital input. when configured as output the output source can be a regi ster bit, or the pwm generator, furtherm ore the output signal can be inverted. integrated active clamp circuits can be enabl ed for the open drain nmos output mode by setting gpioxpulls =11b, thus allowing to use the high current gpio pins for drivin g inductive loads. a pull-up resistor to vcurr_gpio can be enabled for the open drain nmos output mode by setting gpioxpulls =10b. when configured as digital input the logic level ( gpioxinvert =?0?) or the inverted logic level ( gpioxinvert =?1?) of the pin is reflected by bit gpioxbit in the gpio bit register. ! " # $ ! ! ! # !% ! $& ! ! '# $ '' ' " '( '! ) ** + , ' " -, ' "- - - ., ' ". . . /, ' "/ / / 01 $2 ) '( 03% &%% &)) 4 5) .& /6 1 !# $ !# !# ) " ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 31 - 157 as3658 data sheet confidential - detailed description-power management functions moreover, a special function can be selected for each digital input pin and a pull-up resistor to vcurr_gpio or a pull- down resistor can be enabled. table 23. high current gpio pin characteristics (vcurr1_gpi o1 ? vcurr4_gpio4) v vsupply =3.0 to 5.5v; t amb = ?20 to +70c; unless otherwise specified symbol parameter min typ max unit note v gpiomax maximum voltage on curr1...4_gpio 1?4 pins v curr_gpio + 0.3 v pin vcurr_gpio is used as supply for the gpio pins v olh low level output voltage switch mode ?0.3 +0.35 v i ol =+100ma; digital output (gpioxmode=100b and currx_current=3fh) v ol low level output voltage ?0.3 +0.4 v i ol =+1ma; digital output (gpioxmode=000b ... 010b) v oh high level output voltage 0.8v curr_g pio. v curr_gpio v i oh =?1ma; digital push-pull output v il low level input voltage ?0.3 0.4 v digital input v ih high level input voltage 1.3 v curr_gpio v digital input i leakage leakage current 10 a high impedance r pull-up pull-up resistance 78 k gpioxmode =x0b; gpioxpulls =10b; vcurr_gpio=3.6v r pull-down pull-down resistance 161 k digital input; gpioxpulls =01b; vcurr_gpio=3.6v table 24. curr1_gpio1 bit definition addr: 18 gpio1 this register controls the mode of the curr1_gpio1 pin bit bit name default access description 2?0 gpio1mode rom r/w 000 b digi tal open drain nmos output (only nmos enabled) 001b digital push-pull output (nmos & pmos enabled, no pwm out possible) 010b digital input (nmos & pmos disabled, digital input logic enabled) 011b digital open drain current sink operation current defined by curr1_current 100b digital open drain switch operation on resistance defined by curr1_current 101b to 111b high impedance (or sd1 in dcdc step down external controller mode (sd1_1a_mode = 1100b)).nmos & pmos disabled, digital input logic disabled) ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 32 - 157 as3658 data sheet confidential - detailed description-power management functions 4?3 gpio1iosf rom r/w 00b input / output signal is written to or set by gpio1bit in the gpio bit register 01b pwm (o) / wdog (i) if used for pwm, pwm_h_time and pwm_l_time define the high and low time of this output and only allowed for gpio1mode= 011b,100b 10b protection of dcdc stepup1 gpio 1 (o) 11b battery charging eoc indication output gpio 1 (o) if eoc=1 then gpio1=1. dcdc_curr3 is used as output, if curr_gpio1 is used for external dcdc controller 5 gpio1invert rom r/w 0 normal polarity of input / output signal 1 inverted polarity of input / output signal (not possible for pwm out) 7?6 gpio1pulls rom r/w 00b no pull-up or pull-down resistor is enabled in all modes 01b pull-down resistor is enabled in digital input mode (clamp disabled) 10b pull-up resistor is enabled for gpio1mode =000b,010b,011b,100b (clamp disabled) 11b enable active clamp circuit for gpio1mode =000b,010b,011b,100b (pull-up/down disabled) table 25. curr2_gpio2 bit definition addr: 19 gpio2 this register controls the mode of the curr1_gpio2 pin bit bit name default access description 2?0 gpio2mode rom r/w 000b digital open drain nmos output 001b digital push-pull output (no pwm out possible) 010b digital input 011b digital open drain current sink operation current defined by curr2_current 100b digital open drain switch operation on resistance defined by curr2_current 101b to 111b high impedance table 24. curr1_gpio1 bit definition addr: 18 gpio1 this register controls the mode of the curr1_gpio1 pin bit bit name default access description ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 33 - 157 as3658 data sheet confidential - detailed description-power management functions 4?3 gpio2iosf rom r/w 00b input / output signal is written to or set by gpio2bit in the gpio bit register 01b pwm (o) / wdog (i) if used for pwm, pwm_h_time and pwm_l_time define the high and low time of this output and only allowed for gpio2mode= 011b,100b 10b battery charging active indication output gpio2 (o) if battery charging = 1 then gpio2=1 11b na 5 gpio2invert rom r/w 0 normal polarity of input / output signal 1 inverted polarity of input / output signal (not possible for pwm out) 7?6 gpio2pulls rom r/w 00b no pull-up or pull-down resistor is enabled in all modes 01b pull-down resistor is enabled in digital input mode (clamp disabled) 10b pull-up resistor is enabled for gpio2mode =000b,010b,011b,100b (clamp disabled) 11b enable active clamp circuit for gpio2mode =000b,010b,011b,100b (pull-up/down disabled) table 26. curr3_gpio3 bit definition addr: 20 gpio3 this register controls the mode of the curr3_gpio3 pin bit bit name default access description 2?0 gpio3mode rom r/w 000b digital open drain nmos output 001b digital push-pull output (no pwm out possible) 010b digital input 011b digital open drain current sink operation current defined by curr3_current 100b digital open drain switch operation on resistance defined by curr3_current 101b to 111b high impedance 4?3 gpio3iosf rom r/w 00b input / output signal is written to or set by gpio3bit in the gpio bit register 01b pwm (o) / wdog (i) if used for pwm, pwm_h_time and pwm_l_time define the high and low time of this output and only allowed for gpio2mode= 011b,100b 10b gpio3 control of regulators if regx_gpio = 1 and regx_on = 1 11b touchpen adc wait input table 25. curr2_gpio2 bit definition addr: 19 gpio2 this register controls the mode of the curr1_gpio2 pin bit bit name default access description ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 34 - 157 as3658 data sheet confidential - detailed description-power management functions 5 gpio3invert rom r/w 0 normal polarity of input / output signal 1 inverted polarity of input / output signal (not possible for pwm out) 7?6 gpio3pulls rom r/w 00b no pull-up or pull-down resistor is enabled in all modes 01b pull-down resistor is enabled in digital input mode (clamp disabled) 10b pull-up resistor is enabled for gpio3mode =000b,010b,011b,100b (clamp disabled) 11b enable active clamp circuit for gpio3mode =000b,010b,011b,100b (pull-up/down disabled) table 27. curr4_gpio4 bit definition addr: 21 gpio4 this register controls the mode of the curr4_gpio4 pin bit bit name default access description 2?0 gpio4mode rom r/w 000b digital open drain nmos output 001b digital push-pull output (no pwm out possible) 010b digital input 011b digital open drain current sink operation current defined by curr4_current 100b digital open drain switch operation on resistance defined by curr4_current 101b to 111b high impedance 4?3 gpio4iosf rom r/w 00b input / output signal is written to or set by gpio4bit in the gpio bit register 01b pwm (o) / wdog (i) if used for pwm, pwm_h_time and pwm_l_time define the high and low time of this output and only allowed for gpio4mode= 011b,100b 10b gpio4 control of regulators if regx_gpio = 1 and regx_on = 0 11b touchpen dedicated interrupt output 5 gpio4invert rom r/w 0 normal polarity of input / output signal 1 inverted polarity of input / output signal (not possible for pwm out) table 26. curr3_gpio3 bit definition addr: 20 gpio3 this register controls the mode of the curr3_gpio3 pin bit bit name default access description ams ag technical content still valid table 28. gpio signal bit definition addr: 55 gpio signal this register controls the gpio state / status bit bit name default access description www.austriamicrosystems.co m revision 1v13 35 - 157 as3658 data sheet confidential - detailed description-power management functions 7?6 gpio4pulls rom r/w 00b no pull-up or pull-down resistor is enabled in all modes 01b pull-down resistor is enabled in digital input mode (clamp disabled) 10b pull-up resistor is enabled for gpio4mode =000b,010b,011b,100b (clamp disabled) 11b enable active clamp circuit for gpio4mode =000b,010b,011b,100b (pull-up/down disabled) 0 gpio1 0 r/w this bit determines the output signal of the gpio1 pin when selected as output source 1 gpio2 0 r/w this bit determines the output signal of the gpio2 pin when selected as output source 2 gpio3 0 r/w this bit determines the output signal of the gpio3 pin when selected as output source 3 gpio4 0 r/w this bit determines the output signal of the gpio4 pin when selected as output source 4g p i o 1 _ i nn ar this bit reflects the logic level of the gpio1 pin when configured as digital input pin 5g p i o 2 _ i nn ar this bit reflects the logic level of the gpio2 pin when configured as digital input pin 6g p i o 3 _ i nn ar this bit reflects the logic level of the gpio3 pin when configured as digital input pin 7g p i o 4 _ i nn ar this bit reflects the logic level of the gpio4 pin when configured as digital input pin table 27. curr4_gpio4 bit definition addr: 21 gpio4 this register controls the mode of the curr4_gpio4 pin bit bit name default access description ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 36 - 157 as3658 data sheet confidential - detailed description-power management functions the gpio block includes an internal programmable pwm generator (can be connected to any of the gpio1_curr1 ? gpio4_curr4 outputs). its timing is defined by the following tables: table 29. pwm frequency control high time registers addr: 56 pwm frequency control high time registers this register controls the pwm high time bit bit name default access description table 30. pwm frequency control low time registers addr: 57 pwm frequency control low time registers this register controls the pwm low time bit bit name default access description table 31. pwm divider registers bits addr: 58 curr control this register controls the pwm divider bit bit name default access description all step down dcdc converters and several ldos can be directly on/off controlled by curr3_gpio3 or curr4_gpio4. the curr3_gpio3 and/or curr4_gpio4 pin should be set to digital input mode (gpio3mode = 010b, gpio4mode = 010b) and the following register should be set accordingly: 7:0 pwm_h_time 00h r/w t h is bit defines the high time of the pwm generator in 2/fclk_int units 0 pwm_div * 2/ fclk_int 1 pwm_div * 4/ fclk_int 2 pwm_div * 6/ fclk_int .... ffh pwm_div * 512/ fclk_int 7:0 pwm_l_time 00h r/w th is b it defines the high time of the pwm generator in 2/fclk_int units 0 pwm_div * 2/ fclk_int 1 pwm_div * 4/ fclk_int 2 pwm_div * 6/ fclk_int .... ffh pwm_div * 512/ fclk_int 7:6 pwm_div 00h r/w t h is bit defines the divider ratio of the prescaler for the pwm generator 00 divide by 1 01 divide by 2 10 divide by 4 11 divide by 16 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 37 - 157 as3658 data sheet confidential - detailed description-power management functions note: the original digital interface on/off signal is used to switch between curr3_gpio3 and curr4_gpio4; e.g. if ldo_rf1_gpio is set, ldo_rf1_on is (re-)used to selected either curr3_gpio3 (ldo_rf1_on=1) or curr4_gpio4 (ldo_rf1_on=0) as input. table 32. regulator gpio control registers addr: 31 reg gpio ctrl this register enabl es/disables gpio control of the regulators bit bit name default access description 0 ldo_rf1_gpio 0 r/w l do_rf1 on/off control 0 controlled by software (ldo_rf1_on) 1 controlled by curr3_gpio3, if ldo_rf1_on=1 and gpio3iosf=10b controlled by curr4_gpio4, if ldo_rf1_on=0 and gpio4iosf=10b 1 ldo_rf2_gpio 0 r/w ldo_rf2 on/off control 0 controlled by software (ldo_rf2_on) 1 controlled by curr3_gpio3, if ldo_rf2_on=1 and gpio3iosf=10b controlled by curr4_gpio4, if ldo_rf2_on=0 and gpio4iosf=10b 2 ldo_dig1_gpio 0 r/w ldo_dig1 on/off control 0 controlled by software (ldo_dig1_on) 1 controlled by curr3_gpio3, if ldo_dig1_on=1 and gpio3iosf=10b controlled by curr4_gpio4, if ldo_dig1_on=0 and gpio4iosf=10b; do not set ldo_dig1_gpio if dcdc sd1 is in external controller mode (sd1_1a_mode = 1100b) 3 ldo_dig2_gpio 0 r/w ldo_dig2 on/off control 0 controlled by software (ldo_dig2_on) 1 controlled by curr3_gpio3, if ldo_dig2_on=1 and gpio3iosf=10b controlled by curr4_gpio4, if ldo_dig2_on=0 and gpio4iosf=10b do not set ldo_dig2_gpio if dcdc sd1 is in external controller mode (sd1_1a_mode = 1100b) 4 sd1_gpio 0 r/w sd1 on/off control 0 controlled by software (sd1_on) 1 controlled by curr3_gpio3, if sd1_on=1 and gpio3iosf=10b controlled by curr4_gpio4, if sd1_on=0 and gpio4iosf=10b 5 sd2_gpio 0 r/w sd2 on/off control (or sd2 on/off control in 1a mode) 0 controlled by software (sd2_on) 1 controlled by curr3_gpio3, if sd2_on=1 and gpio3iosf=10b controlled by curr4_gpio4, if sd2_on=0 and gpio4iosf=10b ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 38 - 157 as3658 data sheet confidential - detailed description-power management functions 8.4 backup battery charger the backup battery charger operates as a programmable voltage limited current sour ce with a selectable output resistor. it is enabled by setting bbcmode in the backup batter y charger register to a value other than ?00?b and offers the following features: backup battery presence detection selectable output resistor (r bbcout ) to reduce the current at higher voltages programmable charge current i bbc programmable maximum charging voltage v bbc reverse current protection turns off backu p battery charger automatically if v supply www.austriamicrosystems.co m revision 1v13 40 - 157 as3658 data sheet confidential - detailed description-power management functions figure 11. backup battery charger characteristics 5 bbcvolt 0 r/w this value determines the maximum charging voltage v bbc . 0 v bbc =2.5v 1 v bbc =3.0v 6 bbcpwrsave 1 r/w 0 normal operation of the backup battery charger 1 the backup battery charger checks if it is actually charging the battery (bit buchact=?1?) and it is disabled if it is not. every 10s (every 64s in state ?off?) the voltage of the backup battery is checked again to determine if charging is required. this practically reduces the curr ent consumption to 0 if the backup battery is full. 7- - reserved table 34. backup battery charger register addr: 38 backup battery charger this register controls the backup battery charger mode bit bit name default access description i back 400a 200a 100a 50a v back_lim- v delta v back_lim v back rb=0ff rb=0n ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 41 - 157 as3658 data sheet confidential - detailed description-power management functions 8.5 smooth switchover po wer management overview figure 12. power source management architecture the power source management architecture handles the smoo th tran sitions between the two chargers (usb charger on vbus, dcdc step down charger or linear charger on vcharger) and the battery. it takes care about the system power supply v supply and its power requirements. there are following operating conditions possible 1. no charger connected the internal switch s int and the (optional) external switch m batsw are closed and v supply is directly supplied by v bat . because of the very low impedance of the switches the energy losses are minimized. 2. the active charger can deliver more current than the system requires the system is directly supplied by the charger and the rema in ing energy can be used to charge the battery (cc/cv charger). in case of deeply discharge d batteries, the system is always immediat ely started and the internal current source between v supply and v bat delivers the trickle current to the battery. 3. the current limited (e.g. for usb with 500ma) char ge r cannot deliver the current, the system requires in this case, the ideal diode st art s conducting and delivers t he remaining current to the system the transitions between the different power states ar e don e autonomously by the as3658 allowing an uninterrupted operation of the system. the blocks are described in more detail in the following sections. a ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 42 - 157 as3658 data sheet confidential - detailed description-power management functions 8.6 battery switch sint (vsupply, battery) figure 13. battery switch diagram the internal battery switch enables normal operation of the syste m during trickle c harging of a deeply discharged battery. the switch provides the following functions: trickle charging, if v bat is smaller than resvolt. the current is defined in tricklecurrent[1:0] pmos is switched on if v bat is greater then resvolt. constant current charging, if the external charger is in linear operation, or the usb charger is used. the current is defined by constant_current[2:0]. current limitation during tricklecharge, to avoid inrush current: i trickle_ilimit current limitation during constant current charging to avoid inrush current: i cc_ilimit undervoltage protection of vsupply during trickle char ge or constant current charge with linear charger. the charging current is regulated down, if vsupply drops below v supply_min ideal diode operation in isolate battery mode and disabl e charging mode, during charger is unplugged. this operation is for the internal battery switch only. external batt ery switch is open in that mode. regulation will start, if the vsupply voltage drops by more then v diode below the v bat voltage. after three milliseconds debounce time, if no charger is recognized, the internal and external battery switch (if enabled) is closed to have a low ic connection between v bat and vsupply. table 35. battery switch parameters symbol parameter min typ max unit note v supply input voltage 3.0 5.5 v pin vsup_sw1,vsup_sw2 i trickle_limit trickle current limit 400 ma i cc_limit constant current current limit 800 ma current limit in constant current mode (linear charger mode or usb charger only) note: applies only for the battery switch alone ! " # $ % &' # ((( ) *(+ ,- . -- , /0 / /0 /0 1 . !"# !#" # $% $!&"!" !"# ! ' (" ! # ! #) '#*$% + " , - + . ) $// 012.314.3.3 .5 # $%#$ ' (" ! # ! #) ' $% . 6778 ",#9$:!#) !##$ #. $% # ) &#$//#0!%#!$"# ;5 ;#!%# &$ "<="> "" ?#: " ) ""&#= "&#$/#="" ?#&: " ) ="<&:<$!###="<&:< $%#####;, " $! ####### #####################@#############&: " )#$,! ############################ ############## !"#& ! #########################################&: " )# $&% % &<="<&:<" ,<, $" ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 43 - 157 as3658 data sheet confidential - detailed description-power management functions v diode ideal diode start voltage 50 mv v supply_min vsupply level for charging current regulation (reduction), to avoid voltage drop on vsupply -6% 3.9 3% v trickle current (or co nstant current in linear mode) will be regulated down, if vsupply drops below this level 3.6 4.2 4.5 r sw s int p-switch on resistance 0.10 vsup_sw=3.6v table 36. usb-charger bit definitions addr: 10 usb charger control this register controls the mode of the usb charger, and the charger state machine bit bit name default access description 5 dis_batsw_tmp_prot rom r/w 0 over temperature protection of battery switch enabled. (if battery switch is in current source mode, charging is stopped if chip temperature exceeds 110o) 1 over temperature protection of battery switch disabled 7 ext_batsw_en rom r/w 0 external battery switch disabled (pin bat_sw = max(vsupply,v bat )) 1 external battery switch e nabled (pin bat_sw=0v, if status bits batsw_on=1 and batsw_mode=1. these bits are controlled by the charger state machine) table 37. battery switch status bit definitions addr: 100 charger status_usb these bits show the status of the battery switch bit bit name default access description 2 batsw_mode na r 0 trickle charging (or constant current charging in linear mode), if batsw_on=1. external pmos switch disabled 1 switch on battery switch, if batsw_on=1. external pmos switch enabled 3 batsw_on na r 0 battery switch off 1 battery switch on (mode defined by batsw_mode) table 35. battery switch parameters symbol parameter min typ max unit note ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 44 - 157 as3658 data sheet confidential - detailed description-power management functions 8.7 external step down/linear charger the inductive dcdc step down charger (or the extern al linear charger) converts the input voltage from v charger to v supply . the system (dcdc converters, ldos?) are connected directly to v supply ; the ideal diode and the internal battery switch s int (together with the exte rnal battery switch m batsw ) connect v supply to v bat to allow charging of the battery. figure 14. step down charger application diagram with optio nal reverse polarity and short protection if the input voltage can be up to 50v additional three transi stors a nd a simple voltage regulator with a zener diode are required. these circuit ?isolates? the as3658 from the high input voltage and keep the pins vcharger, voff_b and vgate within its operating limits (<15v). the ac tual circuit is shown in the following figure: ! ! "# " $ "# $ " $ " % $ $ & '' ( ( )*+ * * , !% # ! !% # -. !% -. % % !( (& '& % # . / !'0 / $ " !'0 !! $ ' / !'0 $ $ $ & ' / # . ' # $ # 1 / !' 2# ' -0 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 45 - 157 as3658 data sheet confidential - detailed description-power management functions figure 15. charger block diagram for voltages >15v (protection up to 50v; minimum vcharger voltage 8v) instead of using an inductive dcdc step down charger, th e as3658 supports external linear charging mode with an pmos transistor. the operating mode is selected by connecti ng the pin voff_b to gnd (f or 5.5v limited chargers, the usb charger can be used alternatively): ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 46 - 157 as3658 data sheet confidential - detailed description-power management functions figure 16. external linear charger application diagram (voff_b connected to gnd) table 38. charger external components symbol component value note m charger, m batsw, m revpol p-channel mosfet si1403, fdc642p or fdc5614p similar m chrgpu p-channel mosfet bss84 or fdg312p or similar r chrgpu1 pull-up resistor1 2k 5% r chrgpu2 pull-up resistor2 100 5% for m chrgpu =bss84 50 5% for m chrgpu =fdg312p l charger inductor for charging 10h 5v or 6v vcharger input 22h 12v vcharger input d charger diode mbrs130 or pmeg2010 d chrgprot zener diode 5.6v zener diode r chshunt current sense resistor charger 70m 5%, 125mw e.g. vishay dale wsl0805 series r sense current sense resistor 50m 1%, 125mw for i vbat,dc <1.5a e.g. vishay dale wsl0805 series r filter1,2 filter resistor 4.7k 1% can be omitted if fuel gauge and charger functionality is not used c filter filter capacitor 1f 20%, x5r or x7r dielectric c charger bypass capacitor on charger pin 1f 20%, x5r or x7r dielectric + 22f 20%, tantal dielectric ! ! "# " $ "# $ " $ " % $ $ & - 2 3 - 45 6 5 5 a !% # ! !% # 7 8 !% 7 8 % % ! - -& 2 & % # 8 9 ! 2 9 $ " ! 2 !! $ 9 $ $ $ & ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 47 - 157 as3658 data sheet confidential - detailed description-power management functions figure 17. step down charger efficiency (measured) vsupply=4.4v 8.7.1 external step down/linear charger characteristics the battery charge controller co ntrols the external step down / linear charger. during trickle charge of the deeply discharged battery the ste p down/linear converter regulates the vsupply to v chlimit . in step down charger mode, if the v bat voltage exceeds resvoltrise, the intern al battery switch is switched on, the vsupply voltage drops down to v bat immediately, and the step down converte r operates as controlled current source to vsupply. the battery current is regulated to the value defined in constantcurrent register. in linear charger mode, the vsupply is still regulated to v chlimit , if the v bat voltage exceeds resvoltrise. the current is regulated by the battery switch to the valu e defined in the constant current register. in eoc operation (see battery charge controller on page 51) , the operation of the charger depends on the bit isolate_battery: if isolate_battery = 1 and eoc the output is regulated to v chlimit . if isolate_battery = 0 and eoc the out put is not allowed to drop below v eoc (3.6v). c vsupply minimum total capacitance parallel to vsupply 22f 20%, x5r or x7r dielectric 10 h inductor 47f 20%, x5r or x7r dielectric 22 h inductor table 39. step down charger parameters symbol parameter min typ max unit note v rsense_max current limit voltage at rsense 70 100 130 mv e.g.: 1.4a for 0.07o sense resistor typ. c out_10 output capacitor with 10h inductor 20 60 f x7r ceramic table 38. charger external components symbol component value note step down charger 0 10 20 30 40 50 60 70 80 90 100 0,0000 0,2000 0,4000 0,6000 0,8000 1,0000 1,2000 output current (a) efficiency (%) vcharger=5v, f=550khz vcharger=6v, f=550khz vcharger=12v, f=550khz vcharger=5v, f=275khz vcharger=6v, f=275khz vcharger=12v, f=275khz ams ag technical content still valid table 40. step down charger bit definitions addr: 37 step down charger control these bits configures the step down charger bit bit name default access description www.austriamicrosystems.co m revision 1v13 48 - 157 as3658 data sheet confidential - detailed description-power management functions 8.8 usb charger figure 18. usb charger block diagram c out_22 output capacitor with 22h inductor 40 60 f x7r ceramic c out_linear output capacitor in linear mode 20 60 f x7r ceramic l inductor 10/22 h (see table 38) i trickle_limit trickle current limit 400 ma 0 sdc_frequ 0 r/w 0 fclk_int/4 (use as def ault, if vcharger>6v) 1 fclk_int/8 (use as def ault, if vcharger<6v) 1 sdc_pon 1 r/w 0 disable 100% pmos on mode for step down charger 1 enable 100% pmos on mode to reduce voltage drop in low dropout regulation 2 sdc_pass_mode 0 r/w 0 normal mode of step down charger mode 1 step down charger in pass through mode. use this mode with max. 5.5v charger only. vsupply=vcharger in that mode, if no_charging=1. table 39. step down charger parameters symbol parameter min typ max unit note . ! " #$%# &'( )*( + # " ,-. " & -,)'-+ / 0112$ %0 #$%"/ "3 0 4151" 5(15# 1# ,($ 3 %# "3 " 21 ! #$%"4"4 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 49 - 157 as3658 data sheet confidential - detailed description-power management functions the as3658 serves an integrated usb charger for li+ batt eries. the usb charger is a current and voltage limited charger, which can be used to charge li+ ba tteries directly from the usb supply. the v bat voltage limit is set by the register chvolteoc (3.9v ? 4.25v in 50mv steps; identi cal for usb charger and step down charger) and the current limit is set by the register us b_current (94ma to 881ma). the vsupply voltage limit is set to v chlimit during trickle and constant current charging. for usb charging, it is recommended to start with a current limit of 94ma and after negotiates via the usb bus (this ha s to be done by e.g. the uprocessor directly) a differen t current setting can be set to speed up charging (e.g. 470ma). if bit usb_chgen=1 in the boot rom is set, vsupply can start up with usb supply allowing startup from the usb supply . if chen=1 and chdet=1 (external charger enabled and connec ted) the usb_ charger will be deactivated automatically. (the battery charger overrides the usb charger). it's not po ssible to use the internal and the external charger in parallel. end of charge of the usb charger is reache d, if the current th rough the battery falls below the value set in the tricklecurrent [1:0] register. table 41. usb-charger bit definitions addr: 10 usb charger control this register controls the mode of the usb charger, and the charger state machine bit bit name default access description 3:0 usb_current rom r/w se ts the usb input current limit. (0000)b 94ma (usb low current) (0001)b 141ma (0010)b 189ma (0011)b 237ma (0100)b 285ma (0101)b 332ma (0110)b 380ma (0111)b 428ma (1000)b 470ma (usb high current) (1001)b 517ma (1010)b 598ma (1011)b 668ma (1100)b 759ma (1101)b 881ma (1110)b 881ma (do not use) (1111)b 881ma (do not use) 4 usb_chgen rom r/w on/off control of usb charger 0 usb charger disabled. 1 usb charger enabled. ams ag technical content still valid table 42. charger status bit definitions addr:100 charger status_usb these bits show the status of the usb charger bit bit name default access description www.austriamicrosystems.co m revision 1v13 50 - 157 as3658 data sheet confidential - detailed description-power management functions charger detection: the charger will be detected by comparison of th e v_ usb voltage with the vsupply voltage. if v_usb is 50mv higher than vsupply voltage or v_usb > 4.3v or the usb_chdet is set to 1. table 43. usb charger characteristics,vusb=4.3?5 .5v; tamb=?20?+85c; unless otherwise specified. symbol parameter min typ min unit note 5 dis_batsw_tmp_prot rom r/w 0 ove r temperature protection of battery switch enabled. (if battery switch is in current source mode, charging is stopped if chip temperature exceeds 110oc) 1 overtemperature protection of battery switch disabled 6 no_charging rom r/w 0 normal battery charger operation (usb charger and/or step down charger) 1 usb and step down charger is supplying vsupply, but battery switch is open. usb charger or external charger regulate to v chlimit 7 ext_batsw_en rom r/w 0 external battery switch disabled (pin bat_sw= vsupply,v bat ) 1 external battery switch enabled (pin bat_sw=0v, if status bits batsw_on=1 and batsw_mode=1. these bits are controlled by the charger state machine) 0 usb_chdet na r set to 1 if charger is detected 1 u sb_chact na r set to 1 if charger is active 4 ch_overvoltage na r set to 1 if overvoltage on pin vcharger is applied i usbcurrent500ma usbcurrent for 500ma selection 440 470 500 ma resistor on pin rbias to ground of 220k i usbcurrent100a usbcurrent for 100ma selection 84 95 104 ma resistor on pin rbias to ground of 220k table 41. usb-charger bit definitions addr: 10 usb charger control this register controls the mode of the usb charger, and the charger state machine bit bit name default access description ams ag technical content still valid table 44. usb-charger additional trimming addr:130 usb current control this register adds or subtracts current limit bit bit name default access description www.austriamicrosystems.co m revision 1v13 51 - 157 as3658 data sheet confidential - detailed description-power management functions 8.9 battery charge controller the as3658 device serves as a standalone battery charge controller supporting rechargeable lithium ion (li+) and nickel metal hybrid (nimh) batteries. requiring only a few ex ternal components, a full-feat ured battery charger with a high degree of flexibility can easily be realized. the main features of the controller are: charge adapter detection charging of deeply discharged batteries low current (trickle) charging real constant current charging by regulation of the battery current instead of the charge current 2 different top-off charging modes: pulse charging and constant voltage charging fuel gauge enables highly accurate remain ing capacity estimation of the battery overvoltage protection for charge adapter input and main battery battery presence indication operation without battery reverse polarity and short protection charging timout timer battery ntc supervision 8.9.1 charge controller operating modes and building blocks linear step down charger detection the charging circuit automatically detect s, if a step down charger or a linear charger is connected externally, by measuring the voltage on the pin voff_b. if this pin is tied to gnd, the circuit detects a linear charger. otherwise the step down charger is detected charge adapter detection the charge controller uses an integrated detection circuit to determine if an external charge adapter has been applied to the vcharger or v_usb pin. if the adapter volt age exceeds the supply voltage at pin v_supply5 by v chdet the chdet or usb_chdet bit in the charger status register will be set. the detection circuit will reset the charge controller (chdet or usb_chdet is cleared) as soon as the volt age at the vcharger or usb_chdet pin drops to only v chmin 2:0 usb_add_trim_current 00h r/w increase or de crease the usb current limit for additional in system trimming: 100 usbcurrent-5.1% 101 usbcurrent-3.8% 110 usbcurrent-2.5% 111 usbcurrent-1.2% 000 usbcurrent+0% 001 usbcurrent+1.2% 010 usbcurrent+2.5% 011 usbcurrent+3.8% ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 52 - 157 as3658 data sheet confidential - detailed description-power management functions above the battery voltage. in case the as3658 device is reset the charge controlle r will also be reset, even if a charge adapter is applied to the vcharger or v_usb pin. charging deeply discharged batteries to be able to charge even completely discharged batteries the as3658 device contains an internal voltage regulator that uses the voltage of the external charge adapter at pin vcharger or v_usb to generate a bootstrap voltage v 2_5v to supply the internal circuitry necessary for char ging. as soon as the battery voltage exceeds 2.5v, the bootstrap regulator is disabled and the battery voltage will be used to generate the internal supply voltage to supply the charger circuitry. low current (trickle) charging trickle charge mode is started when an external charge a dapter has been detected and ch en or usb_chgen is set, and the battery voltage at pin v_bat is below the resvoltrise threshold v resrise . the battery switch is open in that case (batsw_on=1 batsw_mode=0). bits chact and/or usbchact and trickle will be set in the charger status registers. in this mode the charge curr ent into the battery will be limited to tricklecurrent (set in the charger current register) by the battery switch to prevent undue stress on ei ther the battery or any of the charger components in case of deeply discharged batteries. if vsupply drops below v supply_min threshold the trickle current is regulated down, to keep the vsupply voltage up, even with an curr ent limited charger (e.g.:usb charger). once v resrise has been exceeded, the battery switch will be closed and the charge controller will proceed to c onstant current charge mode. the vsupply voltage of the step down charger will be set to vcurr_preset to prevent undervoltage on vsupply during the transition between trickle and constant current charging. constant current charging constant current charging is initiated by setting bit chen and/or usbchen in the charger control register, and resetting the no_charging bit. note that chen and/or usbchen should be set by default to enable operation of the device without a battery c onnected to the system. the chact and/or usbchact bit is set when the charger has started, and the charge current into the battery will be limited to constantcurrent (set in the charger current register) by the battery charge controller. when the battery approaches full charge, its instantaneous voltage will exceed the charge termination threshold v choff . v choff depends on the chvolteoc .the top-off charge mode will be started (bit cvm will be set). constant voltage charging constant voltage charge mode is initiated and the cvm bit will be set when the v choff threshold has been exceeded for the first time and bit pulse is not set. in the following the charge controlle r will act to regulate the battery voltage to a value set by chvolteoc in the charger config register. the charge current is monitored during co nstant voltage charging. it will be de creasing from its initial value during constant current charging and eventually drop below the value set by tricklecurrent in the charger current register. if the measured charge current is less than or equal to tricklecurrent and the battery voltage is larger than v chres , the charging cycle is terminated and eoc is set. then the charge controller starts the eoc operation. eoc operation there are two possibilities: 1. if isolate_bat=1 the battery switch will be swit ch of f and the battery charger regulates to its highest voltage v chlimit. . the advantage of this mode is a longer lifetime of the li+ battery, because there is no discharging after the eoc condition. if autoresume=1 and the battery voltage drops below v chres the battery charger continues charging, by checking in trickle charge mode, if there is a battery connected, and then starting with constant voltage. 2. if isolate_bat=0 the battery switch remain s closed for step down charger or will be closed for linear and usb charger, and the power to the system is suppl ied by the battery. the battery charge r and the usb charger regulates to v eoc , in case the battery is removed. if autoresume=1 and the battery voltage drops below v chres the battery charger continues charging, by checking in trickle charge mode, if there is a battery connected, and then starting with battery charging. ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 53 - 157 as3658 data sheet confidential - detailed description-power management functions battery detection and restart of charging: in eoc state, if the battery voltage drops below v chres and the bit autoresume is set, the battery detection is started. the battery switch will be swit ched into current source mode and v supply will be regulated to v chlimit (all charger). the as3658 measured the battery current with the fuel gauge in this mode. if there is no current, the as3658 is kept in this state and the bit nobat is set. other wise the bit nobat is cleared and the charger and the as3658 continues in battery charging mode. in addition, if the ntc_on<1:0>=01b (ntc temperature supervision is active) the nobat bit is cleared and charging is restarted, if a ntc resistor with no rmal or high temper ature is detected. overvoltage protection for external linear charger: during charging with the external linear charger th e battery charge controller constantly monitors the voltage of the charge adapter at pin vcharger. in case the charge adapter voltage exceeds v vchin,max rise for longer than 3mesec and bit chovdeten in the charger control register is set to 1, charging is disabled immediately. if the voltage on the pin vcharger drops below v vchin,max fall , the charger is re-enabled. figure 19. typical charging cycle (step down charger) v bat = 2v v supply = 4.4v v charger = 6v v bat = vres_rise (e.g: 3.4v) v supply = 4.4v (isolate_bat=1) v supply = 4.2v (isolate_bat=0) v bat = 4.2v i bat = 0ma i bat = tricklecurrent (e.g 200ma) i bat = constantcurrent (e.g 700ma) constantvoltage eoc ch_det = 0 ch_det = 1 no_charging = 1 no_charging = 0 i2c write ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 54 - 157 as3658 data sheet confidential - detailed description-power management functions figure 20. typical charging cycle (ext ernal linear charger or usb charger) table 45. charger characteristics vvbat=3.0?5. 5v; tamb=?20?+85c; unless otherwise specified symbol parameter min typ min unit note v chlimit voltage limit of charger (if not in current limitation mode) -3% ch_volt age 3% v max. vsupply voltage v charger vcharger operating range 5.0 15.0 v for input voltage higher than 15v see above protection circuit; for chargers with input voltages down to 4.5v see: ?application note for dc/dc step down charger for chargers supplying 4.5v to 5.5v? v chdet charge adapter detection threshold 50 75 105 mv hysteresis is > 40mv; for usb and step down charger v chmin 02035mv v chmin_hold charge adapter detection hold voltage -5 -20 -40 mv vchdet falling threshold, if vsupply>4.35v for v_usb and vcharger, and for v_usb, if usb_hold_chdet=1. warning: backcharging is possible if usb_hold_chdet=1 v chin,max rise charger adapter overvoltage threshold rising 6.0 6.5 7.0 v chovdeten=?1? for external linear charger only v chin,max fall charger adapter overvoltage threshold falling 6.0 v chovdeten=?1? for external linear charger only v bat = 2v v supply = 4.4v..5.0v v charger = 6v v bat = vres_rise (e.g: 3.4v) v supply = 4.4v...5.0v (isolate_bat=1) v supply = 4.2v (isolate_bat=0) v bat = 4.2v i bat = 0ma i bat = tricklecurrent (e.g 200ma) i bat = constantcurrent (e.g 700ma) constantvoltage eoc ch_det = 0 ch_det = 1 no_charging = 1 no_charging = 0 i2c write ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 55 - 157 as3658 data sheet confidential - detailed description-power management functions i startmax maximum load current during startup on vsupply 5ma v uvlo undervoltage lockout threshold ?3% 2.7? 3.4 +3% v value is set by resvoltrise in the battery voltage monitor register v choff charge termination threshold ?0.06 3.90? 4.25 +0.06 v li+ battery; value is set by chvolteoc in the charger config register v chres charger resume voltage 3.85? 4.20 v value is set by chvoltresume in the charger config register. do not set v chres higher than v choff ! v curr_preset charger constant current pre-set voltage v resri se + 100mv v v eoc charger eoc voltage 3.60 v if isolate_bat=0; to prevent a system reset if the battery is removed in eoc operation table 46. charger status bit definitions addr:99 charger status these bits show the status of the charger bit bit name default access description 0c h d e tn ar bit is set when external charge adapter has been detected on pin vcharger 1c h a c tn ar bit is set when step down charger is operating (independent of reg. bit no_charging) 2r e s u m en ar bit is set when battery voltage has dropped below resume level 3 trickle na r bit is set when charger is in trickle charge mode 4c v mn ar bit is set when charger is in top-off charge mode (constant voltage mode) 5e o cn ar bit is set when charging has been terminated. bit is cleared automatically when chen is cleared, no_charging is set or charging is resumed. 6n o b a tn ar bit is set when battery detection circuit indicates that no battery is connected to the system. detection is started after eoc and if bit autoresume=1 only. bit is cleared automatically when a battery is connected, when disbdet is set and/or when chen is cleared. 7 chlinear na r bit is set, if linear charger is detected, and chdet=1. this state is latched on the rising edge of chdet. detected if voff_b is connected to ground table 45. charger characteristics vvbat=3.0?5. 5v; tamb=?20?+85c; unless otherwise specified symbol parameter min typ min unit note ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 56 - 157 as3658 data sheet confidential - detailed description-power management functions table 47. charger control bit definitions addr:11 charger control1 these bits controls the charger bit bit name default access description 0c h e nr o mr / w 0 disable step down charger (independent of bit no_charging) 1 enable step down charger (default) (independent of bit no_charging) 1 ch_pwroff_en rom r/w 0 startup of as3658 if charger is connected in power_off mode 1 don't exit power off mode, if charger is already connected before entering power off mode; no autonomous charging upon static charger detect. startup with rising edge of vcharger or v_usb, rtc wakeup and xon pin only 2 chovdeten rom r/w 0 overvoltage detection with linear external charger enabled 1 overvoltage detection with linear external charger enabled. battery charging disabled, if voltage exceeded 3 autoresume rom r/w 0 charging does not restar t automatically in eoc when bit resume is set. 1 charging will restart automatically in eoc when bit resume is set 4 usb_hold_chdet rom r/w 0 normal charge_detect operation 1 charger detect of usb char ger will not be reset, if vusb=v bat . (allow battery charging, with v_usb<4.4v down to 3.3v); for this case, software should detect the removal of the charger 5 charging_tmax rom r/w 0 read: no timeout reached write: reset charger timeout counter 1 t charging,max timeout reached and charging stopped 6 ch_det_500ms rom r/w controls the charge detect debounce timer on pin vcharger, if external charger is connected. (if the charger is removed the debounce time is always 3msec) 0 v charger debounce timer is 3msec 1 v charger debounce timer is 500msec ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 57 - 157 as3658 data sheet confidential - detailed description-power management functions table 48. battery, supply voltage bit definitions addr:12 battery voltage monitor these bits controls the battery/su pply voltage monitor (reset levels) bit bit name default access description 2:0 resvoltrise rom (101b) r/w this value determines the reset level v resrise for rising v bat . it is recommended to set this value at least 200mv higher than v resfall . 000b v resrise =2.7v 001b v resrise =2.8v 010b v resrise =2.9v 011b v resrise =3.0v 100b v resrise =3.1v 101b v resrise =3.2v 110b v resrise =3.3v 111b v resrise =3.4v 5:3 resvoltfall rom (011b) r/w this value determines the reset level v resfall for falling v vbat . it is recommended to set this value at least 200mv lower than v resrise . 000b v resfall =2.7v 001b v resfall =2.8v 010b v resfall =2.9v 011b v resfall =3.0v 100b v resfall =3.1v 101b v resfall =3.2v 110b v resfall =3.3v 111b v resfall =3.4v 6 supresen rom (0b) r/w 0 a reset is generated if vsupply falls below 2.7v. (if v vbat falls below v resfall only an interrupt is generated (if enabled) and the processor can shut down the system) 1 a reset is generated if vsupply falls below v resfall 7 fastresen rom r/w 0 vresetfall debounce time = 3msec 1 vresetfall debounce time = 4sec ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 58 - 157 as3658 data sheet confidential - detailed description-power management functions 8.9.2 fuel gauge the fuel gauge circuit enables remaining capacity estimation of the battery by tracking the net current flow into and out of the battery using a volt age-to-frequency converter. voltage-to-frequency converter the voltage-to-frequency (vfc) converter constantly monito rs the voltage drop across an external current sense resistor r sense connected in series between the negative batte ry terminal and ground. the use of an additional external rc lowpass filter is highly recommended. using two 4.7k resistors (r filt1,2 ) and a 1f ceramic capacitor (c filt ), the filter cut-off is approx imately 16.9 hz. this filter wi ll capture the effect of most spikes, and will thus allow the current accumulators to a ccurately reflect the total charge that has gone into or out of the battery. table 49. charger config register addr:13 charger config these bits configure the charger bit bit name default access description 2:0 chvolteoc rom sets the end-of-charge voltage level v choff . 000b 3.90v 001b 3.95v 010b 4.00v 011b 4.05v 100b 4.10v 101b 4.15v 110b 4.20v 111b 4.25v 4:3 vsupply_min rom regulate down battery charging current on that level of vsupply during trickle charging and/or linear charging, to prevent voltage drop on vsupply: 00b 3.90v 01b 3.60v 10b 4.20v 11b 4.50v 7:5 chvoltresume rom sets the resume voltage level v chres 000b 3.85v 001b 3.90v 010b 3.95v 011b 4.00v 100b 4.05v 101b 4.10v 110b 4.15v 111b 4.20v ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 59 - 157 as3658 data sheet confidential - detailed description-power management functions the key building block of the vfc is an in tegrator. it will integrate the voltage v sns across input pins isensp and isensn. if v sns is positive (battery is charged), the output voltage of the integr ator increases; a negative input voltage (battery is discharged) will cause the integrator output voltage to decrease. table 50. fuel gauge parameters symbol parameter min typ max unit note charge current accumulator the output signals of the charge count dividers are used as in puts for the charge current accumulator that is realized as a 15-bit up-down counter with separate inputs for incr ementing and decrementing the counter. an additional sign bit indicates the polarity of the counter value that is maintain ed in two?s complement format . the current accumulator is updated at a rate equivalent to one count per 3.05vh, which is equivalent to one count per 61.03ah when using a 50m current sense resistor. it will roll over beyond (7fff) h when incremented and (0000 )h when decremented, and the value given by the counter will be ambiguous in that case. it is the responsibility of t he host to read the counter before rollover occurs. the content of the charge current accumulator will be transferred into the del t acharge register when the updreq bit in the fuelgauge register has been set. the update of the regist er has to be synchronized to the sample clock f vfc and can take up to 1.5 clock cycles (max. 2.5s). af ter the registers have be en updated successfully, the updreq bit is cleared automatically and the char ge current accumulator together with the sign bit will be reset. elapsed time counter the sample clock f vfc of the fuel gauge circuit is fed to a 14-bit clo ck count divider. its output signal is used as a clocking signal for the 16-bit elapsed time counter, resulting in an equivalent rate of 1.1379 counts per second (4096.60 counts = 1 hour). the elapsed time counter will ro llover beyond (ffff)h, and the value given by the counter will be ambiguous in that case. it is the responsibility of the host to read the counter before rollover occurs. the content of the elapsed time counter will be transferred into the elap se dtime register when the updreq bit in the fuelgauge register has been set. the update of the register has to be synchronized to the sample clock f vfc and can take up to 1.5 clock cycles (max. 2.5s). after the registers have been updated su ccessfully, the updreq bit is cleared automatically and the elapsed time counter will be reset. offset calibration mode although the vfc compensates for the offset of the integrator the fuel gauge features an additional offset calibration mode to enhance the measurement accu racy even further. by setting the calreq bit in the fuelgauge register the integrator is reset and the offset calib ration mode is activated. the charge co unt dividers are bypassed during offset calibration to allow a faster calibration procedure with adequat e resolution. the offset is accumulated during 16 clocks of the elapsed time counter, the resulting offset calibration value fgoffcal has a resolution of 3.05v and is f clk internal reference clock f clk_int / 2 mhz internal clk frequency/2 programmable: 0.8 to 1.15 mhz f vfc sample frequency f clk /59 hz v isensp v isensn input voltage -0.1 0.1 v z isensp z isensn input impedance 4.67 m a vfc discharge and charge gain 91.0 hz / v f clk = 1.1mhz fr vfc fundamental rate 3.05 vh v off uncompensated offset voltage -500 500 v v off,comp compensated offset voltage -50 10 50 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 60 - 157 as3658 data sheet confidential - detailed description-power management functions transferred to the deltacharge register. the calreq bit is cleared automatically after the calibration has completed successfully and fgoffcal has been written to the register. please note that offset calibration is not p ossible while the charger is active. if the calreq bit is set while the charger is active the calibration will start automatically after the charger has been disabled by clearing the chen bit or if the external charge adapter has been removed. if during an offset calibration procedu re the charger is enabled the offset calibration mode is terminated, the calreq bit is cleared, the current value of t he elapsed time counter is transferred to the elapsedtime register and the deltacharge register is loaded with (ffff)h. calculation of battery status the host system can calculate all the parameters necessary for estimating the remaining battery capacity by evaluating elapsedtime , deltacharge and fgoffcal . calculating elapsed time the host system can evaluate the change in time t by setting the updreq bit in the fuelgauge register and reading elapsedtime after updreq has been automatically cleared. the ch ange in time in seconds is given by: t = elapsedtime x 3600 / 4096.60 [s] (eq 1) note that the abso lute accuracy of t is directly related to the absolute accura cy of the internal reference oscillator. to cancel the error associated with the accuracy of the oscillato r, a correction factor cv can be introduced. cv can be evaluated by comparing the change in time calculated by (1) with some reference value t ref obtained from a rtc or measured during system calibration. cv is given by: cv = t ref / t( e q 2 ) by multiplying t and cv the correct value for the change in time can be calculated: t corr = cv x t [s] (eq 3) calculating average current the host system can calculate the average current du ring the last time period by setting the updreq bit in the fuelgauge register and reading deltacharge and elapsedtime after updreq has been automatically cleared. together with fgoffcal determined during offset calibration mode the average current is given by: i avg = deltacharge / ( t x a vfc x r sense ) ? fgoffcal x 3.05v / r sense [a] (eq 4) t is the chang e in time in seconds calculated by (1), a vfc is the gain of the vfc in hz/v, r sense is the value of the sense resistor in and f goffcal is the offset calibration value. as deltacharge and t both are proportional to the oscillator frequency, no correction factor needs to be introduced in the formula. calculating accumulated current accumulated current is used to calc u late the absolute remaining capacity of the battery. it is given by: i acc = i avg x t corr [a] (eq 5) calculating the remaining capacity remaining capacity is the entire goal of fuel gauging. it is given by: rc = rc + i acc [as] (eq 6) ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 61 - 157 as3658 data sheet confidential - detailed description-power management functions calculating the time to empty the time to empty is calculated from the average current i avg given by (4). the longer the time period for which i avg is calculated, the more accurate the value for i avg and therefore the estimated time to empty will be. it is given by: tte = rc / i avg [s] table 51. fuel gauge bit definitions addr:15 fuel gauge these bits configures the fuel gauge bit bit name default access description table 52. delta charger msb bit definitions addr:101 deltachargemsb these bits represent the msb value of the fuel gauge delta charge register bit bit name default access description (eq 7) 0 fgen rom r/w 0 disable fuel gauge 1 enable fuel gauge 1 updreq rom r/w this bit controls the update of the deltacharge and elapsedtime registers. when set, the bit is cleared automatically after the registers have been updated successfully. bit should not be set to ?0? by the host 0 update of registers complete 1 request update of registers 2 calreq rom r/w this bit controls the offset ca libration. when set, the bit is cleared automatically after t he calibration has completed successfully. 0 calibration complete or terminate offset calibration 1 request offset calibration 4:3 calmod rom r/w sets the mode for offset calibration 00 connect inputs to ground internally 01 use isensp and isensn (do not use) 10 do not use 11 do not use 6:0 deltachargemsb (00)h r th e register is maintained in two?s complement format with a resolution of 3.05vh and a full-scale value of 99.98mvh. when using a 50m current sense resistor this is equivalent to a resolution of 61.03ah and a full- scale value of 1.999ah. sign is set for negative values. register will be updated after setting bit updreq to ?1?. 7 sign 0 r sign bit of the delta charge register ams ag technical content still valid table 53. deltachargerlsb bit definitions addr:102 deltachargelsb these bits represent the lsb value of the fuel gauge delta charge register bit bit name default access description table 54. elapsedtimemsb bit definitions addr:103 elapsedtimemsb these bits represent the msb value of the fuel gauge elapsed time register bit bit name default access description table 55. elapsedtimelsb bit definitions addr:104 elapsedtimelsb these bits represent the lsb value of the fuel gauge elapsed time register bit bit name default access description www.austriamicrosystems.co m revision 1v13 62 - 157 as3658 data sheet confidential - detailed description-power management functions 8.9.3 charger operation the charger controls the battery curr ent through the internal transistor between vsup_sw1,2 and vbat_sw1,2, the step down charger and the battery switch between vsupply and v bat . charge current regulator the regulator is programmed by setting tricklecurrent and constantcurrent in the chargercurrent register and yields a resolution of 0.625mv or 12.5ma w hen using a sense resistor of 50m . table 56. charge current regulator parameters symbol parameter min typ max unit note 7:0 deltachargelsb (00)h r th e register is maintained in two?s complement format with a resolution of 3.05vh and a full-scale value of 99.98mvh. when using a 50m current sense resistor this is equivalent to a resolution of 61.03ah and a full- scale value of 1.999ah. sign is set for negative values. register will be updated after setting bit updreq to ?1?. 6:0 elapsedtimemsb (00)h r the el apsed time count is st ored in the register with a resolution of 0.8788s and a full-scale value of 15.997 hours. register will be updated after setting bit updreq to ?1?. 7 sign 0 r sign bit of the elapsed time register 7:0 elapsedtimelsb (00)h r th e elap sed time count is stored in the register with a resolution of 0.8788s and a full-scale value of 15.997 hours. register will be updated after setting bit updreq to ?1?. t meas measurement period 68.65 ms f clk_int = 2.2mhz i meas,lsb 0.625 mv ams ag technical content still valid table 57. charger current bit definitions addr:16 charger current these bits define the battery charging current and voltage bit bit name default access description www.austriamicrosystems.co m revision 1v13 63 - 157 as3658 data sheet confidential - detailed description-power management functions 8.10 charger supervision functions the charger supervision functions allow charging without processor control by continuously checking the ntc temperature resistor within the battery pack using adc_in1 pi n. the charging cycle is automatically paused, if the ntc indicates a temperature range out of 0o to 45o (or 0o to 50o). if the temperature gets into this range again the charging cycle is resumed. in addition there is a charge timer th at stops charging after a defined time, as additional security feature. the timer will be reset at charger insert ion (ch arger detect) or at eoc state. the timer is counting during active charging only (trickle charging, constant current charging, constant voltage charging). in case the battery voltage does not reach eoc voltage within t chargingmax after charging has been started, charging_tmax interrupt will be generated and charging will be stopped. charging can be started again by writing charging_tmax=0 in the charger_control1 register. 1:0 tricklecurrent rom r/w sets the trickle current. default is (01)b = 2.5mv x r sense -1 . 00b 1.25mv x r sense -1 01b 2.50mv x r sense -1 10b 5.00mv x r sense -1 11b 10.0mv x r sense -1 4:2 constantcurrent rom r/w sets the charging current in constant current mode from (0mv?35mv) x r sense -1 in steps of 5mv x r sense -1 . 000 0mv x r sense -1 001 5mv x r sense -1 .... 111 35mv x r sense -1 7:5 ch_voltage rom r/w charger voltage after eoc and isolate_battery=1 000b 4.3v 001b 4.4v 010b 4.5v 011b 4.6v 100b 4.7v 101b 4.8v 110b 4.9v 111b 5.0v ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 64 - 157 as3658 data sheet confidential - detailed description-power management functions figure 21. charger supervision functions ? internal circuit table 58. ntc chargersupervision characteristics, vvbat=3.0?5.5v; tamb=?20? +85c; unless otherwise specified. symbol parameter min typ max unit note t sample sample time for ntc measurement high or low temperature 33 ms alternating measurement of the ntc sensor for high temperature and low temperature with two different currents v comp comparator threshold for high and low temperature measurement 1.8 v on pin adc_in1, if ntc_on<1:0>=1 i hightemp45deg_1 0k high temperature current for 45 deg limit, 10k ntc -7% 388 +7% a ntc_type=0, ntc_high_temp=0, @ 1.8v threshold 4.64 k i hightemp50deg_1 0k high temperature current for 50 deg limit, 10k ntc -7% 457 +7% a ntc_type=0, ntc_high_temp=1, @ 1.8v threshold 3.94 k i hightemp0deg_10k high temperature current for 0 deg limit, 10k ntc 60.5 a ntc_type=0 @ 1.8v threshold 29.7 k i hightemp45deg_1 00k high temperature current for 45 deg limit, 100k ntc 39.2 a ntc_type=1, ntc_high_temp=0, @ 1.8v threshold 4.59 k i lowtemp50deg_10 0k low temperature current for 50 deg limit, 100k ntc 46.8 a ntc_type=1, ntc_high_temp=1, @ 1.8v threshold 38.5 k !"# $ % &' %$ ( ( ) *+# )% ,%+# - "# )+# %, .. %, /0 $ 12 * %, ,+3 %, + " " $ % + " %, 4 5 67+ . " %, ,+3 $ , * %, , 8 %, ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 65 - 157 as3658 data sheet confidential - detailed description-power management functions i lowtemp0deg_100 k low temperature current for 0 deg limit, 100k ntc 6.32 a ntc_type=1 @ 1.8v threshold 284 k hystereses ntc current hystereses 4% (approx. 1o .), ntc_hyst=0 8% (approx. 2o.), ntc_hyst=1 i hightempadc_10k current for adc measurement high temp range, 10k ntc -7% 234 +7% a ntc_on<1:0>=2, ntc_type=0, ntc_high_temp=0 i hightempadc_100 k current for adc measurement high temp range, 100k ntc 23.6 a ntc_on<1:0>=2, ntc_type=1, ntc_high_temp=0 i lowtempadc_10k current for adc measurement low temp range, 10k ntc 36 a ntc_on<1:0>=3, ntc_type=0, ntc_high_temp=0 i lowtempadc_100 k current for adc measurement low temp range, 100k ntc 3.7 a ntc_on<1:0>=3, ntc_type=1, ntc_high_temp=0 table 59. charger supervision bit definitions addr:14 charger supervision these bits define charging timer and battery temp. supervision settings bit bit name default access description 3:0 ch_timeout rom r/w charging timeout timer 0000b charging timeout disabled 0001b 1 hour 0010b 1.5 hour 0011b 2 hour 0100b 2.5 hour 0101b 3 hour 0110b 3.5 hour 0111b 4 hour 1000b 4.5 hour 1001b 5 hour 1010b 5.5 hour 1011b 6 hour 1100b 6.5 hour 1101b 7 hour 1110b 7.5 hour 1111b 8 hour 4 auto_shutdown rom 0 (see reset generator and xon-key on page 118) table 58. ntc chargersupervision characteristics, vvbat=3.0?5.5v; tamb=?20? +85c; unless otherwise specified. symbol parameter min typ max unit note ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 66 - 157 as3658 data sheet confidential - detailed description-power management functions 5 ntc_high_temp rom r/w selects the high temp level: 0 45 o maximum temp 1 50o maximum temp low temp is always 0o 6 ntc_hyst rom r/w selects the ntc temperature hysteresis 0 2o hysteresis 1 1o hysteresis 7 ntc_type rom r/w select the ntc resistor type 010k ntc resistor 1 100k ntc resistor table 60. fuelgauge addr:15 fuelgauge this bit controls first star tup out of power on reset bit bit name default access description 7:6 ntc_on rom r/w 00 disable ntc supervision 01 enable ntc supervision 10 enable ntc for adc measurement high temp 11 enable ntc for adc measurement low temp table 59. charger supervision bit definitions addr:14 charger supervision these bits define charging timer and battery temp. supervision settings bit bit name default access description ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 67 - 157 as3658 data sheet confidential - detailed description-power management functions 8.11 step down dc/dc converters 8.11.1 step down dc/dc co nverters operating modes the step down dcdc converters have four operating modes to deliver different output cu rrents for the applications. the operating mode is selected by sett ing the register sdx_1a_mode (the default is set by the boot rom). figure 22. dc/dc step-down sd1, sd2, sd3 normal operating mode; sdx_1a_mode = 0000b figure 23. dc/dc step-down sd1, sd2, sd 3 1a operating mode; sdx_1a_mode = 1010b 77 b ! ""# # !" " " " " " " !" ""# " # ! ! ""# # ! ! ! ! ! ""# # !" " " " " ! ! # " " !" $# " # ! ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 68 - 157 as3658 data sheet confidential - detailed description-power management functions if one of the dcdc step down converters is not us ed for an application, connect it as follows: figure 24. dc/dc step-down sd3 (as example) not used f igure 25. dc/dc step-down sd1, sd2, sd3 extern al controller operating mode; sdx_1a_mode = 1100b note: vcurr_ gpio has to be connected to vsupply if the external controler mode is used. ! 34 5 5 6 !"# $%& # # # # # !"# $%& # # # # ' ' ' ( ) *+ * $%, , &*) (( '- -' . / 0 '- 12 3 ./ 45 .6 7 34627 34 146 2 48 %3 ) * !# ( ) * & ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 69 - 157 as3658 data sheet confidential - detailed description-power management functions figure 26. dc/dc step-down sd1, sd2, sd3 external controller operating mode and sd2 in 1a mode; sd1_1a_mode = 1101b note: the ldo vdig2 and the low voltage current source / gpio pin curr1_gpio1 cannot be used in the ? external controller? oper ating mode configuration. vcurr_gpio has to be connected to vsupply if the external controler mode is used. !"# !%& # ! " %, , & - - . / 0 - 12 3 ./ 45 .6 7 34627 34 146 2 48 %3 !# & # # # # # !"# %& ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 70 - 157 as3658 data sheet confidential - detailed description-power management functions 8.11.2 step down dc/dc converter characteristics figure 27. step down dc/dc converter block diagram functional description the step-down converter is a high efficiency fixed frequency current mode regulator. by using low resistance internal pmos and nmos switches efficiency up to 95% can be ac hieved. the fast switching frequency allows using small inductors, without increasing the current ripple. the uniq ue feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to an output current of 500ma, with an output capacitor of only 10f. the implemented current limitation pr otects the dcdc and the coil during overload condition. to allow optimized performance in different applications, th ere are bit settings possible, to get the best compromise between high efficiency and low input, output ripple: low ripple, low noise operation: bit settings: sdx_dis_curmin=1 in this mode there is no minimum coil current necessary befo re sw itching off the pmos. as result, the on time of the pmos will be reduced down to tmin_on at no or light load cond itions, even if the coil current is very small or the coil current is inverted. this results in a very low ripple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences. because of the inverted coil current in that case the regulator will not operate in pulse skip mode. ! "#! $ $ %& ! ' ' "! ( ) *+,- (. / 0 % - ' ()1 23 % $ 4$ -015657 " ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 71 - 157 as3658 data sheet confidential - detailed description-power management functions figure 28. sdx_dis_curmin=1 operation 1: lx voltage, 2:coil cu rrent (1mv=1ma) 3: vout high efficiency operation (default setting): bit settings: sdx_dis_curmin=0 in this mode there is a minimum coil current necessary befo re switching of f the pmos. as result there are less pulses at low output load necessary, and therefore the efficiency at lo w output load is increased. this results in higher ripple, and noisy pulse skip operation up to a higher output current. figure 29. sdx_dis_curmin=0 operation 1: lx voltage, 2:coil cu rrent (1mv=1ma) 3: v out it?s also possible to switch between these two modes during operation: for example: sdx_dis_curmin=0: system is in idle st ate. no audio, rf signal. decreased supp ly current preferred. increased ripple doesn?t affect syst em performance. sdx_dis_curmin=1: system is operating. audio signal on and/or rf sig nal used. decreased ripple and noise preferred. increased power supply current can be tolerated. ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 72 - 157 as3658 data sheet confidential - detailed description-power management functions 100% pmos on mode for low dropout regulation: for low input to output voltage difference the sdx_dis_pon bit can be set, to allow 100% dut y cycle of the pmos transistor. low power mode: t he sdx_l po mode bit can be set all the time. this mode allows internal power down, of not used blocks during pulseskip mode, which results in a better efficiency at light out put loads. inductor setting: t he step down regulator is optimized fo r 2.2h at 2.2mhz and 4.7h at 1.1mhz table 61. step down dc/dc converter parameters symbol parameter min typ max unit note v in input voltage 3.0 5.5 v pin vsupply_1,vsupply_2, vsupply_3 v out regulated output voltage 0.6 3.3 v v out_tol output voltage tolerance -50 +50 mv output voltage <2.0v -100 +100 mv output voltage >2.0v i limit current limit 800 ma r psw p-switch on resistance 0.5 v_supplyx=3.0v r nsw n-switch on resistance 0.5 v_supplyx=3.0v i load load current 0 500 ma f sw switching frequency 2.2 mhz sdx_frequ=0, f clk_int =2.2mhz 1.1 mhz sdx_frequ=1, f clk_int =2.2mhz eff efficiency 90 % iout=100ma, vout=2.3v, vsup.=3v i vdd current consumption 250 a operating current without load 100 low power mode current 0.1 shutdown current t min_on minimum on time 80 ns t min_off minimum off time 40 ns external components c vsd1-3, c vsd1a output capacitor 8.0 10 f ceramic x5r or x7r c vsupply1-3 input capacitor 2.2 f ceramic x5r or x7r 4.7 f ceramic x5r or x7r; c vsupply1 in external controller mode or 1a operating mode l sd1-sd3 inductor 2.2 h sdx_frequ=0, 10% tolerance 4.7 sdx_frequ=1, 10% tolerance 2.2 sd1 external controller mode; use sd1_freq=1 (1.1mhz) ams ag technical content still valid table 62. step down dc/dc bit definitions addr:35 step down control1 these bits configures the step down converters bit bit name default access description table 63. step down dc/dc bit definitions addr:36 step down control2 these bits configures the step down converters bit bit name default access description www.austriamicrosystems.co m revision 1v13 73 - 157 as3658 data sheet confidential - detailed description-power management functions 0 sd1_psw_on 0 r/w only if sd1_on = 0, switch on psw (0.5 pmos) 1-0n / a 2-0n / a 3 sd1_nsw_on 0 r/w only if sd1_on = 0, switch on nsw (0.5 nmos) 4 sd2_psw_on 0 r/w only if sd2_on = 0, switch on psw (0.5 pmos) 5-0n / a 6-0n / a 7 sd2_nsw_on 0 r/w only if sd2_on = 0, switch on nsw (0.5 nmos) 0 sd3_psw_on 0 r/w only if sd3_o n = 0, switch on psw (0.5 pmos) 1-0n / a 2-0n / a 3 sd3_nsw_on 0 r/w only if sd3_on = 0, switch on nsw (0.5 nmos) 4 sdx_lpo 0 r/w step down low power mode: 0 increased current consumption in pulseskip mode 1 decreased current consumption in pulseskip mode 5 sd1_dis_pon 0 r/w step down pon feature control 0 pon feature enabled: 100% duty cycle (pmos always on) if output voltage drops more than 4%. increased output ripple in that operation. 1 pon feature disabled: maximum dutycycle=1- (tmin_off*fsw) 6 sd2_dis_pon 0 r/w step down pon feature control 0 pon feature enabled: 100% duty cycle (pmos always on) if output voltage drops more than 4%. increased output ripple in that operation. 1 pon feature disabled: maximum dutycycle=1- (tmin_off*fsw) 7 sd3_dis_pon 0 r/w step down pon feature control 0 pon feature enabled: 100% duty cycle (pmos always on) if output voltage drops more than 4%. increased output ripple in that operation. 1 pon feature disabled: maximum dutycycle=1- (tmin_off*fsw) ams ag technical content still valid table 64. step down dc/dc bit definitions addr:37 step down charger control these bits configures the step down converters bit bit name default access description www.austriamicrosystems.co m revision 1v13 74 - 157 as3658 data sheet confidential - detailed description-power management functions 3-0n / a 4 sd1_dis_curmin 0 r/w step down curmin feature control 0 curmin feature enabled: inductor current regulated to min 170ma. higher efficiency in low dropout and low output current operation. higher output ripple and noise. 1 curmin feature disabled: decreased efficiency in low dropout mode and at low output current. small output ripple and noise. 5 sd2_dis_curmin 0 r/w step down curmin feature control 0 curmin feature enabled: inductor current regulated to min 170ma. higher efficiency in low dropout and low output current operation. higher output ripple and noise. 1 curmin feature disabled: decreased efficiency in low dropout mode and at low output current. small output ripple and noise. 6 sd3_dis_curmin 0 r/w step down curmin feature control 0 curmin feature enabled: inductor current regulated to min 170ma. higher efficiency in low dropout and low output current operation. higher output ripple and noise. 1 curmin feature disabled: decreased efficiency in low dropout mode and at low output current. small output ripple and noise. table 65. step down dc/dc reg power1 ctrl bit definitions addr:23 reg power1 ctrl these bits control the on/off function of the step down regulator bit bit name default access description 4 sd1_on rom r/w switch on/off the step down1 dc/dc converter; it is possible to on/off control dcdc sd1 by curr3_gpio3 or curr4_gpio4 (see general purpose input / output (curr1_gpio1 ? curr4_gpio4) on page 30) 0 step down dc/dc 1 off 1 step down dc/dc 1 on 5 sd2_on rom r/w switch on/off the step down2 dc/dc converter; it is possible to on/off control dcdc sd2 by curr3_gpio3 or curr4_gpio4 (see general purpose input / output (curr1_gpio1 ? curr4_gpio4) on page 30) 0 step down dc/dc 2 off 1 step down dc/dc 2 on ams ag technical content still valid table 66. step down voltage1 bit definitions addr:00 step down voltage1 these bits control the step down regulator voltage, frequency, clk phase bit bit name default access description table 67. step down voltage2 bit definitions addr:01 step down voltage2 these bits control the step down regulator voltage, frequency, clk phase bit bit name default access description www.austriamicrosystems.co m revision 1v13 75 - 157 as3658 data sheet confidential - detailed description-power management functions 6 sd3_on rom r/w switch on/off the step down3 dc/dc converter; it is possible to on/off control dcdc sd3 by curr3_gpio3 or curr4_gpio4 (see general purpose input / output (curr1_gpio1 ? curr4_gpio4) on page 30) 0 step down dc/dc 3 off 1 step down dc/dc 3 on 5:0 step_down1_v rom r/w control the voltage selection for the step down1 dc/dc converter 000000 0.6 v ? (lsb=50mv) 111000 ? 11111 3.4 v 6 sd1_frequ rom r/w select the step down1 frequency 0 f clk_int (1.6mhz to 2.3 mhz) 1 f clk_int /2 (0.8mhz to 1.15 mhz) 7 sd1_clkinvert rom r/w inverts the input clock of the step down1 converter 5:0 step_down2_v rom r/w control the voltage selection for the step down2 dc/dc converter 000000 0.6 v ? (lsb=50mv) 111000 ? 11111 3.4 v 6 sd2_frequ rom r/w select the step down2 frequency 0 f clk_int (1.6mhz to 2.3 mhz) 1 f clk_int /2 (0.8mhz to 1.15 mhz) 7 sd2_clkinvert rom r/w inverts the input clock of the step down1 converter table 65. step down dc/dc reg power1 ctrl bit definitions addr:23 reg power1 ctrl these bits control the on/off function of the step down regulator bit bit name default access description ams ag technical content still valid table 68. step down voltage3 bit definitions addr:02 step down voltage3 these bits control the step down regulator voltage, frequency, clk phase bit bit name default access description table 69. step down1 high current and dvm definitions addr:17 charge pump control these bits control the step down high current mode and dvm step size bit bit name default access description www.austriamicrosystems.co m revision 1v13 76 - 157 as3658 data sheet confidential - detailed description-power management functions 5:0 step_down3_v rom r/w control the voltage selection for the step down3 dc/dc converter 000000 0.6 v ? (lsb=50mv) 111000 ? 11111 3.4 v 6 sd3_frequ rom r/w select the step down3 frequency 0 f clk_int (1.6mhz to 2.3 mhz) 1 f clk_int /2 (0.8mhz to 1.15 mhz) 7 sd3_clkinvert rom r/w inverts the input clock of the step down1 converter 3:2 sd1_dvm_time rom r/w t i me step of dvm voltage change of step down1 if voltage of step down1 (ste p_down1_v) is changed during operation, voltage is decreas ed or increased by 25 mv steps with the following time separation between steps: 00 0 sec, immediate change (no dvm) 01 4 sec 10 8 sec 11 16 sec 7:4 sdx_1a_mode rom r/w select 1a mode of step down2 (combined operation of sd2 and sd3 with a single coil and up to 1a output current) and/ or controller mode of sd1 1010 1a mode selected controlled by sd2 the following pins have to be connected: vsupply2<->vsupply3, lx 2<->lx3, pgnd2<- >pgnd3 stepdown3 is not usable in that mode 1100 external controller mode. ldo dig1 and current sink / gpio curr1_gpio1 cannot be used. set ldo_dig1_on=0, gpio1mode=111b (tristate), gpio1pulls=00b (no pull-up or pull-down) 1101 external controller mode sd1, and 1a mode controlled by sd2 the following pins have to be connected: vsupply2<->vsupply3, lx 2<->lx3, pgnd2<- >pgnd3 stepdown3 is not usable in that mode all other codes (0000...1001,1011,1110...1111) normal mode ams ag technical content still valid table 70. step down dc/dc bit definitions addr:133 step down control3 configurate the sd converters to reduce voltage drops on fast transient high current load steps. double the output capacitor size has to be used! bit bit name default access description www.austriamicrosystems.co m revision 1v13 77 - 157 as3658 data sheet confidential - detailed description-power management functions 8.11.3 typical performanc e chara cteristics figure 30. dc/dc step-down efficien cy (sdx_dis_curmin=0, sdx_lpo=0) figure 31. pcb layout recommendation 0 sd1_uvlimit 0 r/w 0 n ormal operation 1 enable sd1 undervoltage limit. 1 sd2_uvlimit 0 r/w 0 normal operation 1 enable sd3 undervoltage limit. 2 sd3_uvlimit 0 r/w 0 normal operation 1 enable sd3 undervoltage limit. ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 78 - 157 as3658 data sheet confidential - detailed description-power management functions 8.12 low dropout re gulators (ldo) the low dropout regulators are linear high perfor mance regulators with pr ogrammable output voltage. they are controlled by the following registers: table 71. ldo_rf1 voltage bit definitions addr:03 ldo_rf1 voltage these bits control the ldo_rf1 voltage and mode bit bit name default access description table 72. ldo_rf2 voltage bit definitions addr:04 ldo_rf2 voltage these bits control the ldo_rf2 voltage and mode bit bit name default access description table 73. ldo_rf3 voltage bit definitions addr:05 ldo_rf3 voltage these bits control the ldo_rf3voltage and mode bit bit name default access description 4:0 ldo_rf1_v rom r/w control th e voltage selection for ldo vrf_1 00000 1.85v ? (lsb=50mv) 11111 3.40v 5 rf1_lcurr_en rom r/w 0 current limitation = ilimit 1 current limitation ilimit=ilimit/2 6 rf1_swprot_en rom r/w if ?1? current limitation is enabled, if rf1-ldo is operating as high side switch 4:0 ldo_rf2_v rom r/w c ontrol th e voltage selection for ldo vrf_2 00000 1.85v ? (lsb=50mv) 11111 3.40v 5 rf2_lcurr_en rom r/w 0 current limitation = ilimit 1 current limitation ilimit=ilimit/2 4:0 ldo_rf3_v rom r/w c ontrol th e voltage selection for ldo vrf_3 00000 1.85v ? (lsb=50mv) 11111 3.40v 5 rf3_lcurr_en rom r/w 0 current limitation = ilimit 1 current limitation ilimit=ilimit/2 6 rf3_hotplug_en rom r/w 0 normal mode 1 200ma current limited switch, if bit rf3_sw=1 (rf3_lcurr_en=0) ams ag technical content still valid table 74. ldo_dig1 voltage bit definitions addr:06 ldo_dig1 voltage these bits control the ldo_dig1 voltage bit bit name default access description table 75. ldo_dig2 voltage bit definitions addr:07 ldo_dig2 voltage these bits control the ldo_dig2 voltage bit bit name default access description table 76. ldo_dig3 voltage bit definitions addr:08 ldo_dig3 voltage these bits control the ldo_dig3 voltage bit bit name default access description table 77. ldo_dig4 voltage bit definitions addr:09 ldo_dig4 voltage these bits control the ldo_dig4 voltage bit bit name default access description table 78. ldos reg power1 ctrl bit definitions addr:23 reg power1 ctrl these bits control the on/off function of the ldo regulator bit bit name default access description www.austriamicrosystems.co m revision 1v13 79 - 157 as3658 data sheet confidential - detailed description-power management functions 5:0 ldo_dig1_v rom r/w control the voltage selection for ldo dig_1 (see table 82) 5:0 ldo_dig2_v rom r/w control the voltage sel e ction for ldo dig_2(see table 82) 5:0 ldo_dig3_v rom r/w control the voltage sel e ction for ldo dig_3(see table 82) 5:0 ldo_dig4_v rom r/w control the voltage sele ction for ldo dig_4(see table 82) 0 ldo_rf1_on rom r/w switch on control of rf1 ldo; important: set rf1_sw=0 before setting ldo_rf1_on=1; it is possible to on/off control ldo rf_1 by curr3_gpio3 or curr4_gpio4 (see general purpose input / output (curr1_gpio1 ? curr4_gpio4) on page 30) 1 ldo_rf2_on rom r/w switch on control of rf2 ldo; important: set rf2_sw=0 before setting ldo_rf2_on=1; it is possible to on/off control ldo rf_2 by curr3_gpio3 or curr4_gpio4 (see general purpose input / output (curr1_gpio1 ? curr4_gpio4) on page 30) 2 ldo_dig1_on rom r/w switch on control of dig1 ldo; it is possible to on/off control ldo dig_1 by curr3_gpio3 or curr4_gpio4 (see general purpose input / output (curr1_gpio1 ? curr4_gpio4) on page 30) 3 ldo_dig2_on rom r/w switch on control of dig2 ld o. do not set if dcdc sd1 is in external controller mode (if sd1_1a_mode = 1100b). it is possible to on/off control ldo dig_2 by curr3_gpio3 or curr4_gpio4 (see general purpose input / output (curr1_gpio1 ? curr4_gpio4) on page 30) ams ag technical content still valid table 79. ldos reg power2ctrl bit definitions addr:30 reg power2 ctrl these bits control the on/off function of the ldo regulator bit bit name default access description www.austriamicrosystems.co m revision 1v13 80 - 157 as3658 data sheet confidential - detailed description-power management functions 8.12.1 rf ldo?s (vrf_1, vrf_2, vrf_3) these ldo?s are designed to supply sensitive analogue circui ts like lna?s, transceivers, vco?s and other critical rf components of cellular radios. another application is the s upply of audio devices or as a reference for ad and da converters. the design is optimized to deliver the be st compromise between quiescent current and regulator performance for battery powered devices. stability is guaranteed with ceramic output capacitors o f 1f 20% (x5r) or 2.2f +100/-50% (z5u) for rf2 , rf3 and 2.2f 20% (x5r) or 4.7f +100/-50% (z5u) for rf1. the low esr of these caps ensures low output impedance at high frequencies. regulation performance is excellent even under low dropout conditions, when the power transistor has to operate in linear mode. power supply rejection is high enough to suppress the pa-ripple on the battery in tdma systems at the output. the low noise performance allows dire ct connection of noise sensitive circuits without additional filtering networks. the lo w impedance of the power device enables the device to deliver up to i out current even at nearly discharged batteries witho ut any decrease of performance. with vrf2_lcurr_en=0 and vrf3_l cu rr_en= 0 the regulator vrf_2, vrf_3 can deliver up to 250ma with vrf1_lcurr_en=0 the regulator vrf_1 can deliver up to 400ma 0 ldo_rf3_on rom r/w switch on control of rf3 ld o; important: set rf3_sw=0 before setting ldo_rf3_on=1 1 ldo_dig3_on rom r/w switch on control of dig3 ldo; it is possible to on/off control ldo dig_3 by curr3_gpio3 or curr4_gpio4 (see general purpose input / output (curr1_gpio1 ? curr4_gpio4) on page 30) ? 2 ldo_dig4_on rom r/w switch on control of dig4 ldo 3 rf1_sw rom r/w if ?1? rf1-ldo is operating as high side switch (ron=1 ), valid if ldo_rf1_on=0 4 rf2_sw rom r/w if ?1? rf2-ldo is operating as high side switch (ron=1 ), valid if ldo_rf2_on=0 7 rf3_sw rom r/w if ?1? rf3-ldo is operating as high side switch (ron=1 ), valid if ldo_rf3_on=0 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 81 - 157 as3658 data sheet confidential - detailed description-power management functions figure 32. analog ldo block diagram table 80. analog ldo (vrf_1, vrf_2, vrf_3) characterist ics, vx_in=4v; iload=150ma; tamb=25oc; cload =2.2f (ceramic); unless otherwise specified symbol parameter min typ max unit note vx_in supply voltage rage 3 5.5 v i out output current 1 01 5 0 ma vrf_2, rf2_lcurr_en=1 vrf_3, rf3_lcurr_en=1 0 200 vrf_1, rf1_lcurr_en=1 02 5 0 vrf_2, rf2_lcurr_en=0 vrf_3, rf3_lcurr_en=0 0 400 vrf_1, rf1_lcurr_en=0 r on on resistance 0.5 vrf_1 1 vrf_2, vrf_3 psrr power supply rejection ratio 70 db f=1khz 40 f=100khz i off shut down current 100 na i vdd supply current 50 a without load noise output noise 50 v rms 10hz < f < 100khz t start startup time 200 s vrf_1,2,3 are set to low current during startup time v out output voltage 1.85 2.85 v vrfx_in>3.0v, vrf_1 @ iout=300ma, vrf_2 and vrf_3 @ iout=150ma (x=1,2) 1.85 3.4 v vrfx_in>3.55v, vrf_1 @ iout=300ma, vrf_2 and vrf_3@ iout=150ma (x=1,2) v out_tol output voltage tolerance -50 50 mv v linereg line regulation -1 1 mv static -10 10 transient; slope: t r =10s !"# $ % & ' ()) * ) ( '+ ), -',, . /.0 00 . /. 1)/ % 2 3 4 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 82 - 157 as3658 data sheet confidential - detailed description-power management functions 8.12.2 digital ldo?s (vdi g_1, vdig_2, vdig_3, vdig_4) the digital ldo?s ca n be used in any medium power system or subsyst em where quiescent power consumption of the regulator itself has to be minimized without sacrificing its performance. for its stability a cheap 1f ceramic capacitor is required. the 5v charge pump will be switched on automa tically, if one of the digital ldo?s are switched on. figure 33. digital ldo block diagram v loadreg load regulation -1 1 mv static -10 10 transient; slope: t r =10s i limit_vrf1_hcur r current limitation 800 ma vrf_1, rf1_lcurr_en=0 i limit_vrf1_lcurr current limitation 400 ma vrf_1, rf1_lcurr_en=1 and during startup i limit_vrf2,3_l current limitation vrf_2,3 low current limit 300 ma rf2_lcurr_en=1, rf3_lcurr_en=1 i limit_vrf2,3_h current limitation vrf_2,3 high current limit 500 ma rf2_lcurr_en=0, rf3_lcurr_en=0 c load_rf1 load capacitor 2 5 f ceramic only (vrf_1) c load_rf2,3_l load capacitor 1 5 f ceramic only (vrf_2,3) for rf1_lcurr_en=1 and rf2_lcurr_en=1 c load_rf2,3_h load capacitor 2 5 f ceramic only (vrf_2,3) for rf1_lcurr_en=0 and rf2_lcurr_en=0 1. guaranteed by design and verified by laboratory evaluation and characterization; not production tested. table 81. digital ldo (vdig1, vdig2, vdig3, vdig4) characteristics,vsupply=4v; iload=200ma; tamb=25oc; cload =1f (ceramic); unless otherwise specified symbol parameter min typ max unit note vdigx_in supply voltage range 1 5.5 v i out output current 1 02 0 0m a v out <2.2v; vdigx_in>v out +r on *i out 01 0 0m a v out <2.5v; vdigx_in>v out +r on *i out r on on resistance 4 v out <2.2v table 80. analog ldo (vrf_1, vrf_2, vrf_3) characterist ics, vx_in=4v; iload=150ma; tamb=25oc; cload =2.2f (ceramic); unless otherwise specified symbol parameter min typ max unit note ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 83 - 157 as3658 data sheet confidential - detailed description-power management functions psrr power supply rejection ratio 60 db f=1khz 30 f=100khz i off shut down current 100 na i vdd supply current 20 a without load t start startup time 200 s v out output voltage 0.75 2.20 v vsupply>3.0v, vcp=5.2v, iout<200ma 2.5 v vsupply>3.0v, vcp=5.2v, iout<100ma v out_tol_lv output voltage tolerance -50 50 mv vout<1.85v v out_tol_hv output voltage tolerance -60 60 mv vout>1.85v v linereg line regulation -10 10 mv static -50 50 transient; slope: t r =10s v loadreg load regulation -20 20 mv static -50 50 transient; slope: t r =10s i limit current limitation 400 ma 1. guaranteed by design and verified by laboratory evaluation and characterization; not production tested table 81. digital ldo (vdig1, vdig2, vdig3, vdig4) characteristics,vsupply=4v; iload=200ma; tamb=25oc; cload =1f (ceramic); unless otherwise specified symbol parameter min typ max unit note ams ag technical content still valid table 82. digital ldo (vdig_1.4) programming voltage table code (d) code (b) v out (v) code (d) code (b) v out (v) www.austriamicrosystems.co m revision 1v13 84 - 157 as3658 data sheet confidential - detailed description-power management functions note: full performance for vout 2.20v; max. 100ma output current for vout 2.50v; do not use values vout>2.50v 8.12.3 low power ldo (v2_5) the low power ldo v2_5 is needed to supply the chip core (analog and digital) of the device. it is designed to get the lowest possible power consumption, and still offering reas onable regulation characteristics. the regulator has three supply inputs selecting automatically the higher one. this gives the possibility to supply the chip core either with the battery or with the charger depending on the conditions. bulk switch comparators are used to avoid any parasitic current flow. to ensure high psrr and stability, a low-esr ceramic capacitor of min. 1f must be connected to the output. 0 000000 0.75 22 010110 1.80 1 000001 0.80 23 010111 1.80 2 000010 0.85 24 011000 1.80 3 000011 0.90 25 011001 1.80 4 000100 0.95 26 011010 1.80 5 000101 1.00 27 011011 1.80 6 000110 1.05 28 011100 1.80 7 000111 1.10 29 011101 1.80 8 001000 1.15 30 0 11110 1.80 9 001001 1.20 31 011111 1.80 10 001010 1.25 32 100000 1.50 (do not use) 11 001011 1.30 33 100001 1.60 (do not use) 12 001100 1.35 34 100010 1.70 (do n0t use) 13 001101 1.40 35 100011 1.80 (do not use) 14 001110 1.45 36 100100 1.90 15 001111 1.50 37 100101 2.00 16 010000 1.55 38 100110 2.10 17 010001 1.60 39 100111 2.20 18 010010 1.65 40 101000 2.30 19 010011 1.70 41 101001 2.40 20 010100 1.75 42 101010 2.50 21 010101 1.80 table 83. low power ldo (v2_5) characteristics, v bat =4v; iload_ext=0; tamb=25oc; cload =2.2 f (ceramic); unless otherwise specified symbol parameter min typ max unit note v bat supply voltage rage 2.8 5.5 v v charger 41 5 r on on resistance 50 guaranteed per design psrr power supply rejection ratio 60 db f=1khz 40 f=100khz ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 85 - 157 as3658 data sheet confidential - detailed description-power management functions 8.13 5v charge pump figure 34. 5v charge pump block diagram the charge pump uses the pad vcp_in as input, regulates an d d oubl es its voltage with the help of the flying capacitor between capp and capn to its output vcp_out (the output is automatically limited not to exceed v cpout ). if the bit cp_pulseskip is set, the char ge pump operates in pulse skip mode, and only starts cycles if its output voltage is below this level. in this mode the supply current is reduced, but the output ripple is increased. the charge pump requires the following external components: table 84. charge pump external components symbol parameter min typ min unit note i off shut down current 100 na i vdd supply current 3 a guaranteed per design, consider chip internal load for measurements. t start startup time 200 s v out output voltage 2.4 2.5 2.6 v v out_tol output voltage tolerance -50 50 mv v linereg line regulation -10 10 mv static -50 50 transient; slope: t r =10s v loadreg load regulation -10 10 mv static -50 50 transient; slope: t r =10s c fly external flying capacitor 370 470 850 nf ceramic x5r or x7r low-esr capacitor between capp and capn c store external storage capacitor 1.76 2.2 2.64 f ceramic x5r or x7r low-esr capacitor between vcp_out and vss dout schottky diode for startup between vcp_in and vcp_out 1 a peak current of schottky diode table 83. low power ldo (v2_5) characteristics, v bat =4v; iload_ext=0; tamb=25oc; cload =2.2 f (ceramic); unless otherwise specified symbol parameter min typ max unit note 5 5 5 5 5 ! " #$ % ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 86 - 157 as3658 data sheet confidential - detailed description-power management functions make the connections of the external capacitors as short as possible. table 85. charge pump characteristics symbol parameter min typ max unit note table 86. cp power1 ctrl bit definitions addr:23 reg power1 ctrl these bits control the on/off fu nction of the ldo regulator bit bit name default access description table 87. charge pump bit definitions addr:17 charge pump control these bits control the charge pump bit bit name default access description v cpin charge pump input voltage 3.0 5.5 v f in switching frequency 1.1 mhz cp_freq=0, f clk_int =2.2mhz 0.55 mhz cp_freq=1, f clk_int =2.2mhz i cpout output current 0.0 100 ma vcp_in = 3.2v, clock = f clk_int /2; cp_pulseskip=0; f in =1.1mhz v cpout output voltage 4.9 5.2 5.6 v v cpskip output voltage during pulseskip 4.92 v use with cp_frequ=1 only i cp_noload supply current without load 2 ma 1.1mhz switching frequency i cp_pulseskip charge pump supply current without load in pulseskip mode 20 a cp_pulseskip=1 and cp_frequ=1 7 cp_on rom r/w switch on of the charge pump block, charge pump is automatically activa ted if any of the following blocks are active: vdig_1, vdig_2, vdig_3, vdig_4 0 cp_pulseskip rom r/w sw it ches on the pulseskip mode of the charge pump 0 normal fixed frequency mode 1 pulse skip, low power mode (set cp_frequ=1 in this mode) 1 cp_freq rom r/w defines the clock frequency of the step up dc/dc converter 0 f clk_int /2 (0.8 to 1.15 mhz) 1 f clk_int /4 (0.4 to 0.575 mhz) ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 87 - 157 as3658 data sheet confidential - detailed description- audio functions 9 detailed description- audio functions the audio functions consist of all the audio features of as3658 as shown in the following block diagram: figure 35. as3658 au dio functions 9.1 audio paths following audio paths are possible (only one c onfiguration is possible at the same time): figure 36. as3658 i2s i/o 1 or i2s i/o2 playback note: as the touch screen interface is merged with i2s ou tput 3 and spdif ou tput 4 either the touch screen interface or i2s output 3 and spdif ou tput 4 can be used at the same time. ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 88 - 157 as3658 data sheet confidential - detailed description- audio functions figure 37. as3658 line in recording figure 38. as3658 microphone recording it is also possible to use the audio adc and the audio dac at the same time. in this case, the sampling frequency of the audio dac is either two or four times the sampling rate of the audio adc (adc: max. 16ks / seconds). the equalizer should not be used in this case: ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 89 - 157 as3658 data sheet confidential - detailed description- audio functions figure 39. as3658 microphone recording and i2s i/o playback (either i2s 1 or i2s 2/pcm) figure 40. as3658 recording of the mixed output signal and parallel playback (either i2s 1 or i2s 2/pcm) 9.2 common mode voltage gene ration of hp_cm, line_cm the common mode voltage of the headphone and lineout is stored in the c_hpcm and c_linecm capacitor (connected between hp_cm to vss and line_cm to vss). thes e capacitor are also responsible for the popless startup, psrr of the amplif iers and sense path of the gnd cancellation circuit. startup and psrr is defined by the value of the external cap a citors. the rc limits the maximum achievable psrr: r=6m typ, c=0.1...1f: table 88. common mode voltage, audio start-up and psrr capacitor value for c_hpcm and c_linecm startup time (typ) maximum achievable psrr @ 1khz (typ) @ 100hz (typ) f msec db db 0.1 1 50 76 56 1 1500 90 76 ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 90 - 157 as3658 data sheet confidential - detailed description- audio functions 9.3 audio setup registers audio ldo has to be switched on first (aud_ldo_on=1), and enables all other functions. table 89. audioset1 register addr:74 audio set1 these bits control the audio functions bit bit name default access description 0 lin_on 0 r/w 0 l ine input disabled 1 line input enabled 1 dac_on 0 r/w switch on control of audio dac 0 dac disabled 1 dac enabled (switch on, if i2s signal valid only) 2 mix_on 0 r/w 0 mixer switched off 1 mixer switched on 3 gnd_sw_on 0 r/w 0 gnd switch off 0v at pin gnd_sw 1 gnd switch on vsupply at pin gnd_sw 4 aud_ldo_on 0 r/w audio ldo on control 0 audio ldo off 1 audio ldo on 5 mclk_invert 0 r/w mclk invert selection 0 change of lrclk at falling edge of mclk 1 change of lrclk at rising edge of mclk 6 mclk256 0 r/w 0 mclk = lrclk* 128 1 mclk = lrclk* 256 7 equ_on 0 r/w 0 equalizer switched off (bypassed) 1 equalizer switched on table 90. audioset2register addr:75 audio set2 these bits control the audio functions bit bit name default access description 1,0 ibr_dac<1:0> 00b r/w bias current reductio n settings for dac: 00 default 01 don't use 10 don't use 11 don't use 2 dith_on 0 r/w 1 add dither to the audio stream 0 no dither added 3 i2s_3_on 0 r/w 0 switch off i2s_3 output 1 switch on i2s_3 output ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 91 - 157 as3658 data sheet confidential - detailed description- audio functions 9.4 adc, dac and di gital audio input 9.4.1 general digital audio data can be fed into the as3658 via the i2s in terface this input data is used by the 18-bit dac to generate the analog audio signal. the stage is set to mute by default; if the dac input is not enabled. 9.4.2 signal description the digital audio interface uses the standard i2s format: left justified msb first one additional leading bit mclk has to have a fixed ratio of 128 or 256 to lrclk. wi th a lrclk equal to 16, 32, 44.1 or 48khz, the mclk can be generated by the on-chip pll (do not use the internal pll if there is jitter on the lrclk1 or 2). for lower sample rates the bit pll_mode has to be set (for sample rates between 8khz and 12khz). the high going edge of mclk has to have timing separati on from lrclk edges. if the cl ock generation is so that lrclk edges are at the same time as mclk high going edges, the mclk can be inverted to guarantee a proper dac function. this audio input interfaces uses an i2s synchronizer to be able to handle audio sample length of 24bits or less. 5,4 ibr_hph<1:0> 0 r/w bias current reduction settings for headphone output 00 0% 01 17% 10 34% 11 50% 6 i2s_select 0 r/w 0 select i2s_1 input 1 select i2s_2 input 7 i2s_mclk_en 0 r/w 0 generation of the master clock by the internal pll 1 use pin mclk_1, mclk_2 as masterclock input table 90. audioset2register addr:75 audio set2 these bits control the audio functions bit bit name default access description ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 92 - 157 as3658 data sheet confidential - detailed description- audio functions figure 41. i2s control diagram figure 42. i2s timing diagram table 91. pll,mclk settings i2s_mclk_en i2s_select mclk_invert description 000 i2s_1 selected (pll used) internal mclk synchronized to external lrclk 001 i2s_1 selected (pll used) internal lrclk used, synchronized to external sdi 010 i2s_2 selected (pll used) internal mclk synchronized to external lrclk 011 i2s_2 selected (pll used) internal lrclk used, synchronized to external sdi sdi1 sclk1 lrclk1 mclk1 sdi2 sclk2 lrclk2 mclk2 sdo3 sclk3 lrclk3 i2s _s elec t 0 1 i2s _s elec t 0 1 sdo1 i2s _s elec t 0 1 i2s _s elec t 0 1 i2s_master_on 0 1 m clk divider i2s_clk_divider<11:0> pll rising edge only for p cm com patibility pll_mode 18 bit dac mono to stereo conversion for pcm_mode=1 sdo sclk lrclk mclk 14 bit adc sdi sclk lrclk mclk equalizer * 256 * 64 i2s_lrck_sclk_out_en i2s_master_on fadc2 pcm_mode samle_rate 0 0 lrclk / 2 1 0 lrclk / 4 0 1 lrclk sample rate sclk_invert sclk_invert lrclk_out i2s_lrck_sclk_out_en i2s_master_on *2 mclk256 ext_mclk i2s _mc lk _en mclk_invert 0 1 0 1 mclk_invert i2s_lrck_sclk_out_en i2s_master_on sdo_on_mclk1_en sdo sdo3_select 0 1 0 1 0 1 mclk_invert i2s_mclk_out_en i2s_master_on i2s_3_on spdif spdif_ctrl<1:0> audio left a udio right audio left audio right spdif i2s_mclk_en 15 2 1 0 17 2 1 0 left channel 15 2 1 0 17 2 1 0 right channel lrck sclk sdata 16 bit sdata 18 bit mclk 64 cycles 64 cycles ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 93 - 157 as3658 data sheet confidential - detailed description- audio functions 9.4.3 parameter table 92. audio dac/adc parameter parameter min typ max unit table 93. i2s parameter i2s inputs and outputs vi2s=2.9v min typ max table 94. dac_l register addr:77 dac_l these bits control the audi o dac volume and functions bit bit name default access description 1 0 0 i2s_1 selected, external mclk on mclk_1 1 0 1 i 2s_1 selected, external mclk on mclk_1 (inverted) 1 1 0 i2s_2 selected, external mclk on mclk_2 1 1 1 i2s_2 selected, external mclk on mclk_2 (inverted) analog performance pro g rammable gain dac input -43.43 1.07 db programmable gain adc input -34.5 12 db gain step size 1.5 db dac thd+noise at fs -85 -75 db dac sn/r (20hz-20khz, -60dbfs) a-weighted 90 94 db dac inter channel mismatch 0.25 db adc sn/r 82 db vil sclkx, lrclkx, sdix - - 0.42v vih s clkx, lrclkx, sdix 1.02v - 3.3v vol sdox,sclk3,lrclk3,spd if,sclk1,lrclk1,mclk1 0v voh sdox,sclk3,lrclk3,spd if,sclk1,lrclk1,mclk1 vi2s 4:0 dal_vol 00000b r/w volume settings for left dac input, adjustable in 32 steps @ 1.5db 00000 -40.5 db gain 00001 -39 db gain ..... 11110 4.5 db gain 11111 6 db gain 5--- 6 dac_mute_off 0 r/w 0 dac input is set to mute 1 normal operation table 91. pll,mclk settings i2s_mclk_en i2s_select mclk_invert description ams ag technical content still valid table 95. dac_r register addr:78 dac_r these bits control the audi o dac volume and functions bit bit name default access description table 96. adc_l register addr:79 adc_l these bits control the audi o adc volume and functions bit bit name default access description www.austriamicrosystems.co m revision 1v13 94 - 157 as3658 data sheet confidential - detailed description- audio functions 4:0 dar_vol 00000b r/w volume settings for right dac input, adjustable in 32 steps @ 1.5db 00000 -40.5 db gain 00001 -39 db gain ..... 11110 4.5 db gain 11111 6 db gain 4:0 adl_vol 00000b r/w volume settin gs for left adc input, adjustable in 32 steps @ 1.5db 00000 -34.5 db gain 00001 -33 db gain ..... 11110 10.5 db gain 11111 12 db gain 5 adc_on 0 r/w 0 adc disabled 1 adc enabled 6 adc_mute_off 0 r/w 0 adc input is set to mute 1 normal operation 7 ad_fs2 0 r/w divider selection for adc clock 0 adc sample clock is i2s lrclk / 2; every adc sample is sent twice to the i2s output (up- sampling by 2) 1 adc sample clock is i2s lrclk / 4; every adc sample is sent four times to the i2s output (up- sampling by 4) ams ag technical content still valid table 97. adc_r register addr:80 adc_r these bits control the audi o adc volume and functions bit bit name default access description www.austriamicrosystems.co m revision 1v13 95 - 157 as3658 data sheet confidential - detailed description- audio functions 9.5 i2s master mo de and pcm mode the digital audio interface can also operat e in master mode by using i2s1 interface. the pin mclk2 is used as clock input in that case. any input clock between sampling rate and 24mhz may be used as input clock. in m aster mode operation sc lk1 as output has 32 clock cycl es for each sam ple word. sclk = [mclk / 4] = [lrclk * 256 / 4] = lrck * 64 (eq 8) sample rates in master mode the i2smaster control allows programming va rious sa mple rates. the master clock is generated from the mclk2 input. sampling frequencies from 8khz to 48khz can be selected. for certain division ratios between master clock and sample ratio a certain deviation is system inherent. 4:0 adr_vol 00000b r/w volume setti ngs for right adc input, adjustable in 32 steps @ 1.5db 00000 -34.5 db gain 00001 -33 db gain ..... 11110 10.5 db gain 11111 12 db gain 5 adc2dac 0b r/w 0 normal mode 1 use adc output as dac input (for testing purposes, equalizer is bypassed) 7:6 adcmux 00b r/w 00 microphone 01 line in 10 reserved ?do not use 11 audio sum (output of mixer) table 98. pll,i2s_clk_divider settings sample rate mclk2 input divider i2s_clk_divider <10:0> actual sample rate error khz khz khz % 2 1 * 2 1 * 2 + = rd flrclk mclk 48,000 1228 8 126,00 126 48,00 0,00 44,100 1228 8 137 ,32 137 44,20 0,23 32,000 12288 190,00 190 32,00 0,00 29,400 12288 206,98 207 29,40 -0,01 24,000 12288 254,00 254 24,00 0,00 22,050 12288 276,64 277 22,02 -0,13 12,000 12288 510,00 510 12,00 0,00 ams ag technical content still valid table 99. i2s master control1 register addr:131 i2s master control1 this register controls the external clock divider for i2s master mode bit bit name default access description www.austriamicrosystems.co m revision 1v13 96 - 157 as3658 data sheet confidential - detailed description- audio functions 11,025 12288 555,28 555 11,03 0,05 8,000 12288 766,00 766 8,00 0,00 48,000 12000 123,00 123 48,00 0,00 44,100 12000 134,05 134 44,12 0,04 32,000 12000 185,50 186 31,91 -0,27 29,400 12000 202,08 202 29,41 0,04 24,000 12000 248,00 248 24,00 0,00 22,050 12000 270,11 270 22,06 0,04 12,000 12000 498,00 498 12,00 0,00 11,025 12000 542,22 542 11,03 0,04 8,000 12000 748,00 748 8,00 0,00 7:0 i2s_clk_divider<7:0> 00h r/w bit 7:0 of divider for mclk2 input pin table 100. i2s master control2 register addr:132 i2s master control2 this register controls the external cl ock divider and modes for i2s master mode bit bit name default access description 2:0 i2s_clk_divider<10:8> 000b r/w bit 10:8 of divider for mclk2 input pin 3 i2s_master_on 0b r/w 0 i2s master mode disabled 1 i2s master mode enabled 4 i2s_lrclk_sclk_out_en 0b r/w 0 lrclk1 and sclk1 are used as input (slave mode) 1 lrclk1 and sclk1 are used as output (master mode). clock input for pll is mclk2 5 i2s_mclk_out_en 0b r/w 0 mclk1 used as input (slave mode) 1 mclk1 used as output for master clock of an external i2s. clock input for pll is mclk2 (mclk1=256*lrclk, if bit mclk256=1; mclk=128*lrclk, if bit mclk256=0) 6 sdo_on_ mclk1 0b r/w 0 normal operation of mclk1 (input or output according to bit is2_mclk_out_en bit) 1 mclk1 used as sdo output (e.g. for audio adc). may be used as data output (sdo) for i2s_2 port table 98. pll,i2s_clk_divider settings sample rate mclk2 input divider i2s_clk_divider <10:0> actual sample rate error khz khz khz % ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 97 - 157 as3658 data sheet confidential - detailed description- audio functions 9.5.1 pcm mode settings compatible with bluecore3-rom: figure 43. short frame sync (shown with 16-bit sample) the following setup on pcm-master side is needed: as3658 is slave only pcm_sync is in short frame mode pcm_sync rate is 8ksamples/s pcm_clk= 512khz only (64 x pcm_sync) 16 bit linear coding of pcm_out and pcm_in (msb first, lsb last) mono (single channel) operation only. only the right channel of the as3658 is used. the left channel is same as right channel (in the input direction of as3658) and has to be ignored by pcm master (in output direction of as3658) note: internally the right channel is copied to the right and left channel. the following setup of as3658 is needed: sclk_invert=1 i2s_mclk_en=0 and mclk_invert=1 (internal pll used for generation of internal lrclk) pcm_mode=1 and ad_fs2=0 (necessary to allow unsymme trical lrclk and sample rate of 8khz of adc) 7 pcm_mode 0b r/w 0 normal i2s mode 1 pcm mode selected. the following additional settings are necessary to enable pcm mono mode: sclk_invert=1 i2s_mclk_en=0 and mclk_invert=1 (internal pll used for generation of internal lrclk) table 100. i2s master control2 register addr:132 i2s master control2 this register controls the external cl ock divider and modes for i2s master mode bit bit name default access description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 in short frame sync the falling edge of pcm_sync indicate the st art of the pcm word. pcm_sync is always one clock cycle long. pcm_sync pcm_clk pcm_out undefined undefined pcm_in lrclk sclk sdi sdo ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 98 - 157 as3658 data sheet confidential - detailed description- audio functions 9.6 line input 9.6.1 general as3658 includes one stereo single ended inputs. figure 44. linein block diagram table 101. line inputs parameter parameter min typ max unit analog performance rin 50 k table 102. line_in_r register addr:85 line_in_r these bits control the line_in volume and functions bit bit name default access description 4:0 lir_vol 00000b r/w volume settings for right line input, adjustable in 32 steps @ 1.5db; gain from line input pin (lin1r) to mixer input 00000 -34.5 db gain 00001 -33 db gain ..... 11110 10.5 db gain 11111 12 db gain 5 mute_off_inr 0 r/w control of mute switch 0 right line input is set to mute 1 normal operation 7:6 - - do not change !" # " "$%" " $%" & ' ( & ' ( ams ag technical content still valid www.austriamicrosystems.co m revision 1v13 99 - 157 as3658 data sheet confidential - detailed description- audio functions 9.7 five band equalizer the 5 band equalizer is build of one low pass, one high pass and 3 band pass filter, and is optimized for 44.1khz sample frequency: low pass filter: 200hz ( when programming negaitve gai n values, this filter changes to a hp filter) band pass filter1: 340hz / q=1.0 (when programming negative gain values, this filter changes to a notch filter) band pass filter2: 1100hz / q=0.7 (wh en programming negative gain values, this filter changes to a notch filter) band pass filter3: 3375hz / q=1.0 (when programming negative gain values, this filter changes to a notch filter) high pass filter: 5940hz (when pragramming negative gai n values, this filter changes to a lp filter) the q factors and the cut off frequency of the high and lo w p ass filter are measured at 50% gain and are valid for +6db amplification of each band. the attenuation or amplificatio n of each b and can be dynamically adjusted by the serial interface. additional a pre-gain stage can adjust the input level. this gain stage is after the 16 to 24 bit extension and therefore additional gain, which is compensated with the equaliz er filter itself (eq_lp_gain, eq_band1,2, 3_gain, eq_hp_gain) will not cause clipping: figure 45. equalizer block diagram table 103. line_in_l register addr:86 line_in_l these bits control the line_in volume and functions bit bit name default access description 4:0 lil_vol 00000 r/w volume settings for right line input, adjustable in 32 steps @ 1.5db; gain from line input pin (lin1l) to mixer input 00000 -34.5 db gain 00001 -33 db gain ..... 11110 10.5 db gain 11111 12 db gain 5 mute_off_inl 0 r/w control of mute switch 0 left line input is set to mute 1 normal operation 7:6 00 n/a do not change ! ams ag technical content still valid www.austriamicrosystems.com revision 1v13 100 - 157 as3658 data sheet confidential - detailed description- audio functions figure 46. eq filter frequency response sum curve figure 47. eq filter frequency response +12db/+6db/+3db ams ag technical content still valid www.austriamicrosystems.com revision 1v13 101 - 157 as3658 data sheet confidential - detailed description- audio functions figure 48. eq filter frequency response -3db each band has a range from -12 to +12 db with each increment equal to 3db. for sample frequencies of the i2s stream different from 44.1khz, the filter frequencies are shifted (ratiometric). table 104. eq_lp register addr: 90 eq_lp these bits control the gain of the low pass filter in db bit bit name default access description 3:0 eq_lp_gain 0000b r/w eq_ l p filter gain (-12db... +12db) 0h 0db 1h 3db 2h 6db 3h 9db 4h 12db bh -3db ch -6db dh -9db eh -12db ams ag technical content still valid table 105. eq_band1 register addr: 91 eq_band1 these bits control the gain of the band pass filter1 in db bit bit name default access description table 106. eq_band2 register addr: 92 eq_band2 these bits control the gain of the band pass filter2 in db bit bit name default access description www.austriamicrosystems.com revision 1v13 102 - 157 as3658 data sheet confidential - detailed description- audio functions 3:0 eq_band1_gain 0000b r/w eq_band1 filter gain (-12db... +12db) 0h 0db 1h 3db 2h 6db 3h 9db 4h 12db bh -3db ch -6db dh -9db eh -12db 3:0 eq_band2_gain 0000b r/w eq_band2 filter gain (-12db... +12db) 0h 0db 1h 3db 2h 6db 3h 9db 4h 12db bh -3db ch -6db dh -9db eh -12db ams ag technical content still valid table 107. eq_band3 register addr:93 eq_band3 these bits control the gain of the band pass filter3 in db bit bit name default access description table 108. eq_hp register addr:94 eq_hp these bits control the gain of the high pass filter in db bit bit name default access description www.austriamicrosystems.com revision 1v13 103 - 157 as3658 data sheet confidential - detailed description- audio functions 3:0 eq_band3_gain 0000b r/w eq_band3 filter gain (-12db... +12db) 0h 0db 1h 3db 2h 6db 3h 9db 4h 12db bh -3db ch -6db dh -9db eh -12db 3:0 eq_hp_gain 0000b r/w eq_hp filter gain (-12db... +12db) 0h 0db 1h 3db 2h 6db 3h 9db 4h 12db bh -3db ch -6db dh -9db eh -12db ams ag technical content still valid table 109. eq_preamp register addr:95 eq_preamp these bits control the preamplifier of the eq in db bit bit name default access description www.austriamicrosystems.com revision 1v13 104 - 157 as3658 data sheet confidential - detailed description- audio functions 4:0 eq_pre_gain 00000b r/w eq_vol gain (-12db ... +12db with 1.5db steps) 0h 0db 01h -1.5db 02h -3.0db 03h -4.5db 04h -6.0db 05h -7.5db 06h -9.0db 07h -10.5db 08h -12db 09h 1.5db bh 3.0db ch 6.0db dh 7.5db eh 9.0db fh 10.5db 10h 12db ams ag technical content still valid www.austriamicrosystems.com revision 1v13 105 - 157 as3658 data sheet confidential - detailed description- audio functions 9.8 microphone input general the audio front-end offers one microphone inputs and a low noise microphone voltage supply (microphone bias), voice activation, microphone connect detec tion and push button remote control. figure 49. microphone input block diagram and external circuit gain stage & limiter the integrated pre-amplifier allows 3 preset gain settings. there is also a limiter which attenuates high input signals from e.g. electret microphones signal to 1vp. the agc has 15 steps with a dynamic range of about 29db. the agc is on by default but can be disabled by a microphone register bit. apart from the microphone pre-amplifie r th e microphone input signal can further be amplified with 32 @1.5db programmable logarithmic gain steps and mute. all gains and mute are independently programmable. the gain can be set from ?40.5db to +6db. the stage is set to mute by default. if the microphone input i s not enabled, the volume settings are set to their default values. changing the volume and mute control can only be done after enabling the input. supply & detection the microphone input generates a supply voltage of 1.5v above agnd. the supply is designed for 2ma and has a 10 ma current limit. in off mode the mics terminal is pulled to avdd with 30k . a current of typically 50 a generates an interrupt to inform the cpu, that a circuit is connected. when using the mics terminal as adc-10 input to monitor external voltage the 30k pull-up can be disabled. remote control fast changes of the supply current of typically 500a are detected as a remote button press, and an interrupt is generated. voice activation further a built-in voice activation compar ator can actuate an interrupt if micro phone input voltage of about 5mvrms is detected. ! "#!$# "!$# % &'() * ) *+, " ! "-!.. /0 11 /0 12/ /0& /03 /0& && / /03 11 / /04 11 / /0 &&1/ /05 &&1/ 31 ) !.. 6 "# . 17 ams ag technical content still valid www.austriamicrosystems.com revision 1v13 106 - 157 as3658 data sheet confidential - detailed description- audio functions microphone input parameter table 110. microphone inputs parameter, ta= 25oc unless otherwise mentioned symbol parameter min typ max unit note v micin 0 input signal level 40 mv peak a micpre = 28db; a mic = 0db v micin 1 20 mv peak a micpre = 34db; a mic = 0db v micin 2 10 mv peak a micpre = 40db; a mic = 0db r micin input impedance 15 k micp, micn to agnd micin input impedance tolerance 15 % c micin input capacitance 5 pf a micpre microphone preamplifier gain 28 db preamplifier has 3 selectable (fixed) gain settings 34 40 a mic programmable gain -40.5 +6 db gain steps 1.5 db discrete logarithmic gain steps gain step precision 0.25 db v miclimit limiter activation level 1 v peak a miclimit limiter gain overdrive 15*2 db t attack limiter attack time 50 s/6db t decay limiter decay time 120 ms/6db a micmute mute attenuation 100 db v micsup microphone supply voltage 2.9 v i micmax max. microphone supply current 10 ma microphones nominally need a bias current of 0.5ma-1ma v noise microphone supply voltage noise 5v i micdet microphone detection current 50 a i remdet max. remote detection current 500 a ams ag technical content still valid www.austriamicrosystems.com revision 1v13 107 - 157 as3658 data sheet confidential - detailed description- audio functions register description table 111. mic_r register addr:87 mic_r right microphone input register configures the gain from microphone amplifier output bit bit name default access description 4:0 mr_vol 00000b r/w volu me settings for right microphone input, adjustable in 32 steps @ 1.5db; gain from microphone amplifier 00000 -40.5 db gain 00001 -39 db gain ..... 11110 4.5 db gain 11111 6 db gain 6:5 pre_gain 00 r/w sets the gain of the microphone preamplifier 00 gain set to 28 db 01 gain set to 34 db 10 gain set to 40 db 11 reserved, do not use 7 mic_agc_off 0 r/w control of limiter agc (automatic gain control). limits high dynamic range of electret/mems microphone (e.g. user shouts or blows into microphone) 0 automatic gain control enabled 1 automatic gain control disabled table 112. mic_l register addr:88 mic_l left microphone input register configures the gain from microphone amplifier output bit bit name default access description 4:0 ml_vol 00000 r/w volume settings for left microphone input, adjustable in 32 steps @ 1.5db; gain from microphone amplifier 00000 -40.5 db gain 00001 -39 db gain ..... 11110 4.5 db gain 11111 6 db gain 5 rdet_off 0 r/w disables the microphone detect function (30k pull-up from mics to vdac) to use the terminal as adc-10 input 0 microphone detection enabled 1 microphone detection disabled 6 mute_off 0 r/w control of mute 0 microphone input set to mute 1 gain set to 34 db ams ag technical content still valid www.austriamicrosystems.com revision 1v13 108 - 157 as3658 data sheet confidential - detailed description- audio functions 9.9 audio output mixer 9.9.1 general the mixer stage sums up the audio signals of the following stages microphone input line input digital audio input (dac) the mixing ratios have to be with the volume registers of the co rresponding input stages. please be sure that the input signals of the mixer stage are not higher than 1vp. if summing up several signals, each individual signal has of course to be accordingly lower. this shall insure that the output signal is also not higher than 1vp to get a proper signal for the output amplifier. this stage features an automatic gai n control (agc), which aut omatically avoids clipping. 9.9.2 register description 7 msup_off 0 r/w 0 microphone supply on if mic_on=1 1 microphone supply off table 113. audioset_3 register addr:76 audio_set3 register configures the mixer inputs and agc bit bit name default access description 0 pll_mode 0 r/w preset of pll bias for the following sampling frequencies 0 16-48ks 1 8-12ks 1 hp_pulld_en 0 r/w controls the pulldown of the hp1 if hp2is enabled and hp2, if hp1 is enabled 0 pulldown disabled if hp_on=1 1 pulldown of the not used hp1/2 output enabled, if hp_on=1 2 voxm_on 0 r/w switches on the voice recognition 0o f f 1o n 3 mic_on 0 r/w switches on the microphone amplifier 0o f f 1o n table 112. mic_l register addr:88 mic_l left microphone input register configures the gain from microphone amplifier output bit bit name default access description ams ag technical content still valid www.austriamicrosystems.com revision 1v13 109 - 157 as3658 data sheet confidential - detailed description- audio functions 9.10 line output 9.10.1 general the line output is designed to provide the audio signal on 600 min. this output stage has an independent gain regulation for le f t and right channel with 32 steps @ 1.5db each. the gain can be set from ?40.5db to +6db. 9.10.2 no-pop function to avoiding click and pop noise during power-up and shutdown, the output is automatically set to mute when the output stage is disabled. also the volume settings are set to thei r default values, and can?t be changed, as long the output stage is not enabled. line_cm pin, which needs a 0.1f... 1f capacitor outside gets charged on power-up with 1a to alvdd/2. after st art-up the dc level of the following pins are the sa me: lout_l=lout_r=line_cm= alvdd/2. the start-up time before releasing mute is about 150ms with 0.1f. to av oid pop-noise 150ms discharging time of line_cm after a shutdown, have to be waited before starting up again. 9.10.3 ground noise cancellation the purpose of the ground cancellation circuit is to com pensate noise (ground noise) between different grounds (e.g. the ground where the as3658 is soldered vers us e.g. the ground of a car amplifier (see figure 50) ). this noise between these different grounds can be caused e.g. by a high current dev ices like a motor-fan. the ground cancellation circuit can be used for line and headphone amplifiers. the circuit works as follows: the ground noise gets added inside the as3658 to the audio sig nal (input line_cm for the line out amplifier or hp_cm for headphone amplifier) in a way that it cancels inside the car amplifier. the sense point is connected with r gnd_sep (20 ) to the battery ground. 4 agc_off 0 r/w switches the signal limiter off 0 automatic gain control for summing stage enabled 1 automatic gain control for summing stage disabled 5 dacmix_off 0 r/w input from dac to r and l 0o n 1o f f 6 micmix_off 0 r/w input from microphone to r and l 0o n 1o f f 7 linmix_off 0 r/w input from line input to r and l 0o n 1o f f table 113. audioset_3 register addr:76 audio_set3 register configures the mixer inputs and agc bit bit name default access description ams ag technical content still valid www.austriamicrosystems.com revision 1v13 110 - 157 as3658 data sheet confidential - detailed description- audio functions the ground cancellation can be disabled by shorting the 20 resistor setting bit gnd_sw to ?1?. this bit should be set if e.g. a headphon e instead of the car amplif ier is connected to the output jack. note: a similar cicuit can be used for the headphone amplifier. f igure 50. ground noise cancellation application schematic 9.10.4 power save options to save power, a reduction of the bias current can be selected. table 114. line power-save options ibr_line idd_line (typ.) 9.10.5 parameter 02 . 2 m a 11 . 5 m a table 115. line out block characteristics parameter min typ max unit analog performance r_ loa d at lout_l and lout_r single ended 600 gain step precision (rlmin-max,20hz-20khz) 0.5 db sinad no load, linein-> line out, a-weighted -97 db thd @ 1khz, no load -88 db thd @ 1khz, 600 -80 db psrr (200hz-20khz) 60 90 db iout_powerdown -20 20 a tpower_up (c_linecm=100nf) 150 ms 4 ! " ## !$ % & ' ( ( % ") ") *+,- ).( & ' & /00 1 (2 & & /00 1 3&! & %/4( %/4( ).( ''+- %/4 *+,- %/4 *+,- ")( .0 '+5 %/4 6785 %/4 6785 ")( .0 -)97' & '#',- ")( : ams ag technical content still valid www.austriamicrosystems.com revision 1v13 111 - 157 as3658 data sheet confidential - detailed description- audio functions 9.10.6 register description to get an interrupt on an over-current event, the corresponding bit in the interrupt enable register has to be set. all other line/headphone driver settings are controlled by the following two registers. right line register table 116. line_out_r register addr:83 line_out_r these bits control the line in volume and mode bit bit name default access description gnd cancellation gnd - audio_gnd to lout _r, l out_l no load 100hz 50 db 1khz 50 10khz 40 4:0 liner_vol 00000b r/w volume settings for right line output, adjustable in 32 steps @ 1.5db 00000 -40.5 db gain 00001 -39 db gain ...... 11110 4.5 db gain 11111 6 db gain 5 dac2line_on 0 r/w 0 line_out amplifier input connected to mixer output 1 line_out amplifier input connected to audio dac output gain stage (mixer is bypassed in this mode) 7:6 ibr_line<1:0> 00b r/w bias current reduction settings for line output: 00 0% 01 17% 10 34% 11 50% table 115. line out block characteristics parameter min typ max unit ams ag technical content still valid www.austriamicrosystems.com revision 1v13 112 - 157 as3658 data sheet confidential - detailed description- audio functions left line register table 117. line_out_l register addr:84 line_out_l these bits control the line in volume and mode bit bit name default access description 9.11 headphone output the headphone output is designed to provide the audio signal with 2x40mw @ 16 or 2x20mw @32 , which are typical val ues for headphones. this output stage has an independent gain regulation for le f t and right channel with 32 steps @ 1.5db each. the gain can be set from ?40.5db to +6db. 9.11.1 phantom ground hp_cm_pwr pin is the buffered hp_cm output. it can be used to drive the common mode level with a load of 2k . the pha ntom ground can be switched off to save power if not needed. 9.11.2 no-pop function to avoiding click and pop noise during power-up and shutdown, the output is automatically set to mute when the output stage is disabled. also the volume settings are set to thei r default values, and can?t be changed, as long the output stage is not enabled. hp_cm pin, which needs a 100nf to 1f capacitor outside , g e ts charged on power-up with 1a to avdd/2. after start- up the dc level of the following pins are the same: hpr=hpl=hp_cm=hp_cm_pwr=av dd/2. the start-up time before releasing mute is about 150ms. to avoid pop-noise 150ms discharging time of hp_cm after a shutdown, have to be waited before starting up again. 9.11.3 over-current protection this output stage has an over-current pr otection, which disables t he output for 256ms or 512ms. this value can be set in the headphone registers. the over-current protection limit of hpr and hpl pin is about 260ma while hp_cm_pwr pin has a 370ma limit. 4:0 liner_vol 00000b r/w volume settings for left line output, adjustable in 32 steps @ 1.5db 00000 -40.5 db gain 00001 -39 db gain ...... 11110 4.5 db gain 11111 6 db gain 5 - 0 reserved 6 line_on 0 r/w 0 line stage not powered 1 power up line stage 7 line_mute 0 r/w 0 normal operation 1 line output set to mute (mute is on during power-up) ams ag technical content still valid www.austriamicrosystems.com revision 1v13 113 - 157 as3658 data sheet confidential - detailed description- audio functions 9.11.4 power save options to save power, especially when driving 32 loads, a reduction of the bias current can be selected. bias current reduction settings for headphone output: 00: 0% 01: 17% 10: 34% 11: 50% 9.11.5 parameters table 118. power amplifier parameter parameter min typ max unit 9.11.6 register description to get an interrupt on an over-current event, the correspondi ng bit in the interrupt enable register has to be set. changing the bias current or the output driver strength is done via audioset 2 register. all other headphone driver settings are controlled by the following two registers. analog performance r_l oad at aoutr and aoutl single ended 16 vout 1.13 vp gain step precision (rlmin-max,20hz-20khz) 0.5 db sinad no load, linein-> hph, a-weighted -97 db thd @ 1khz, no load -88 db thd @ 1khz, 32 , 10mw -80 db thd @ 1khz, 32 , 20mw -74 -66 db thd @ 1khz, 16 , 40mw -68 -60 db channel separation (32 , dc-coupled) 60 db psrr (200hz-20khz) 60 90 db shorted protection level 260 ma shorted protection level of common mode buffer 370 ma iout_powerdown -20 20 a tpower_up (hp_cm=0.1f) 150 ms gnd cancellation gnd - audio_gnd to hp_r, hp_l no load 100hz 50 db 1khz 50 10khz 40 ams ag technical content still valid www.austriamicrosystems.com revision 1v13 114 - 157 as3658 data sheet confidential - detailed description- audio functions right headphone register table 119. hph_out_r register addr:81 hph_out_r these bits control the right headphone ouput volume and mode bit bit name default access description left headphone register table 120. hph_out_l register addr:82 hph_out_l these bits control the left headphone ouput volume and mode bit bit name default access description 4:0 hpr_vol 00000b volu me settings for right headphone output, adjustable in 32 steps @ 1.5db 00000 -40.5 db gain 00001 -39 db gain ...... 11110 4.5 db gain 11111 6 db gain 5 hpcm_off headphone phantom ground disable 0 normal operation 1 disable common mode buffer 7:6 hp_ovc_to 00h headphone over current time out: speaker over current time out: 00 256 ms 01 128 ms 10 512 ms 11 0 ms 4:0 hpl_vol 00000b volume settings for left headphone output, adjustable in 32 steps @ 1.5db 00000 -40.5 db gain 00001 -39 db gain ...... 11110 4.5 db gain 11111 6 db gain 5 hp_mux 0 r/w 0 use hpl1, hpr1 as headphone output 1 use hpl2, hpr2 as headphone output 6 hp_on 0 r/w 0 headphone stage not powered 1 power up headphone stage 7 hp_mute 0 r/w 0 normal operation 1 headphone output set to mute (mute is on during power-up) ams ag technical content still valid www.austriamicrosystems.com revision 1v13 115 - 157 as3658 data sheet confidential - detailed description- audio functions 9.12 spdif output enables and controls the spdif output pin. spdif functional ity is enabled, if internal masterclock is used (internal pll), or the external masterclock = 256* lrclk. (no spdif function if external masterclock= 128 *lrclk) table 121. spdif register addr:89 spdif these bits control the spdif output bit bit name default access description 1:0 spdif_cntr 00b r/w ispdif output on/off control and sample rate status bits 00 spdif output off 01 spdif output on 10 reserved (do not use) 11 reserved (do not use) 2 spdif_invalid 0 r/w spdif sample status bit 0 sample valid 1 sample invalid 3 spdif_mclk_inv 0 r/w spdif master clock control bit 0 master clock 1 master clock inverted 4 spdif_copy_ok 0 r/w spdif copy control bit 0 copy not permitted 1 copy permitted 5 sdo3_select 0 r/w select source of sdo3 output 0 select adc_output 1 select equalizer output 6 sclk_invert 0 r/w invert serial data clo ck of i2s1 and i2s2 0 normal mode 1 invert sclk1 or sclk2 input 7 audio_off 0 r/w switch off audio functionality for low power touchpannel detection 0 normal mode 1 audio bias switched off to reduce power ams ag technical content still valid www.austriamicrosystems.com revision 1v13 116 - 157 as3658 data sheet confidential - detailed description - system functions 10 detailed description - system functions the system functions consist of the i2c in terface, the reset controller, the inte rrupt controller, st artup sequences and programming, the watchdog, internal references, th e on-key detect and the real time clock module. 10.1 i 2 c serial interface table 122. i2c sda,scl characteristics symbol parameter min typ max unit note 10.1.1 feature list fast-mode capability (max. scl-frequency is 400 khzkhz) 7+1-bit addressing mode 60h x 8-bit data registers (word address 0x00 - 0x60) write formats: single-byte-write, page-write read formats: current-address-read, random-read, sequential-read sda input delay and scl spike f iltering by integrated rc-components 10.1.2 transfer formats figure 51. i 2 c byte-write as3658 device address write (dw):80h = 10000000b as3658 device address read (dr): 81h = 10000001b figure 52. i 2 c page-write: byte-write and page-write are used to write data to the slave. v il scl,sda low level input voltage -0.3 0.4 v v ih scl,sda high level input voltage 1.3 vsupp ly v s dw a wa a reg_data a p write register, wa++ s start condition after stop sr repeated start dw device address for write dr device address for read wa word address aacknowledge n no acknowledge p stop condition white field slave as receiver grey field slave as transmitter wa+ + increment word address internall y s dw a wa a reg_data 1 a a reg_data 2 write register wa++ p a reg_data n write registe r wa++ write registe r wa++ ? ams ag technical content still valid www.austriamicrosystems.com revision 1v13 117 - 157 as3658 data sheet confidential - detailed description - system functions the transmission begins with the start condition, which is generated by the master when the bus is in idle state (the bus is free). the device-write address is followed by the word address. after the word address any number of data bytes can be send to the slave. the word address is incrimi nated internally, in order to write subsequent data bytes on subsequent address locations. for reading data from the slave device, the master has to ch ange the transfer direction. this can be done either with a repeated start condition followed by the device-read address, or simply with a new transmission start followed by the device-read address, when the bus is in idle state. the device-read address is always followed by the 1 st register byte transmitted from the slave. in read-mode any number of subsequent register bytes can be read from the slave. the word address is incriminated internally. the diagrams below show various read formats available: figure 53. i 2 c random-read: random-read and sequential-read are combined formats. the repeated start condition is used to change the direction after the data transfer from the master. the word address transfer is initiated with a start condition issued by the master while the bus is idle. the start condition is followed by the device-write address and the word address. in order to change the data direction a repeated start condition is issued on the 1 st scl pulse after the acknowledge bit of the word address transfer. after t he reception of the device-read address, the slave becomes the transmitter. in this state the slave transmits register data located by the previous received word address vector. the master responds to the data byte with a not-acknowledge, and issues a stop condition on the bus. figure 54. i 2 c sequential-read: sequential-read is the extended form of random-read, as more th an one register-data bytes are transferred subsequently. in difference to the random-read, for a se quential read the transferred register-data bytes are responded by an acknowledge from the master. the number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-addr ess counter). to terminate the transmission the master has to send a not- acknowledge following the last data byte and generate the stop condition subsequently. a s dw a wa a data n p read register wa++ sr dr wa++ a s dw a wa a data 1 n p sr dr wa++ ? data 2 data n a a read register wa++ ams ag technical content still valid www.austriamicrosystems.com revision 1v13 118 - 157 as3658 data sheet confidential - detailed description - system functions figure 55. i 2 c current-address-read: to keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. the bus is idle and the ma ster issues a start condition followed by the device-read address. analogous to random-read, a single byte trans fer is terminated with a not-acknowledge after the 1 st register byte. analogous to sequential-read an unlim ited number of data bytes can be trans ferred, where the data bytes has to be responded with an acknowledge from the master. for te rmination of the transmission the master sends a not- acknowledge following the last data byte and a subsequent stop condition. 10.2 reset generator and xon-key xreset is a low active bi-directional pin. an exter nal pull-up to the periphery supply has to be added. during each reset cycle the following st ates are controlled by the as3658: pin xreset is forced to gnd programmable power-off function programmable power-on sequence and regulator voltages programmable reset timer all registers are set to their default values after po wer-on, except the reset c ontrol- and status-registers. note: programmin g is controlled by the internal ma sk-prom and the external resistor rprogram table 123. xreset,xon characteristics symbol parameter min typ max unit note 10.2.1 reset conditions reset can be activated from 7 different sources: power on (battery or charger insertion) low battery software forced reset power off mode external triggered through the pin reset overtemperature watchdog v xreset_il xreset low level input voltage -0.3 0.4 v v xreset_ih xreset high level input voltage 1.3 vsupp ly v v xon_il xon low level input voltage -0.3 0.3*v2 _5 v xon_ih xon high level input 0.7*v2 _5 v2_5 i xon_pup xon pull up current 12 a a data 1 read register wa++ s dr data 2 a read register wa++ n p wa++ ? data n a read register wa++ ams ag technical content still valid www.austriamicrosystems.com revision 1v13 119 - 157 as3658 data sheet confidential - detailed description - system functions voltage detection: there are two types of voltage dependent resets: v por and v xreset . v por monitors the voltage on v2_5 and v xreset monitors the voltage on vsupply. the linear regulator for v2_5 is always on and uses the voltage vcharger, v bat or v_usb as its source. the pin reset is only released if v2_5 is above v por and vsupply is above vxreset rise . table 124. reset levels symbol parameter min typ max unit note vreset falling is only accepted if the rese t condition is longer than vreset mask . this guard time is used to avoid a complete reset of the system in case of short drops of v bat . power off: to put the chip into ultra low power mode, write ?1? into xon_enable and ?1? into power_off . the chip stays in power off mode until the external pin xon is pulled lo w, the charger is inserted or the level v por is touched to start a complete reset cycle. the bit power_off is automatically cleared by this reset cycle. during power_off state all circuits are shut-off except the low power ldo (v2_5). thus the current consumption of as3658 is reduced to less than 15 a. the digital part is supplied by v2_5, all other circuits are turned off in this mode, including references and oscillator. except the reset control registers all other registers are set to their default value after power-on. software forced reset writing ?1? into the re gister bit force_reset immediatel y starts a reset cycle. the bit force_reset is automatically cleared by this reset. external triggered reset: if the pin xreset is pulled from high to low by an external source (e.g. mi croprocessor or button) a reset cycle is started as well. overtemperature reset: the reset cycle can be started by overtemperature conditions. (see protection functions on page 134) watchdog reset: if the watchdog is armed (register bit wtdg_on = 1 and wtdg_res_on = 1) and the timer expires it causes a reset. (see watchdog on page 135) . v por overall power on reset 1.5 2.0 2.3 v monitor voltage on v2_5; power on reset for all internal functions vxreset rise reset level for vsupply rising resvol trise v monitor voltage on vsupply; rising level vxreset falling reset level for vsupply falling 2.7 v monitor voltage on vsupply; falling level resvol tfall v if supresen=1 only vreset mask mask time for vxreset falling 2.0 2.5 3.0 ms duration for v bat www.austriamicrosystems.com revision 1v13 121 - 157 as3658 data sheet confidential - detailed description - system functions 6:3 reset_reason na r flags to indicate to the software the reason for the last reset 0000 v por has been reached (battery or charger insertion from scratch) 0001 vreset falling was reached (battery voltage drop below 2.75v) 0010 software forced by force_reset 0011 software forced by power_off and xon was pulled low 0100 software forced by power_off and charger was detected 0101 external triggered through the pin reset 0110 reset caused by overtemperature t 140 0111 reset caused by watchdog 1000 reset caused by 5 seconds on press 1001 reset caused by rtc_alarm register 1010 reset caused by rtc repeated wakeup 1011 reset caused by interrupt in standby mode 1100 reset caused by xon pulled low in standby mode 7 onkey_reset_5s 1 r/w 0 reset after 5 seconds on pressed disabled 1 reset after 5 seconds on pressed enabled table 127. internal references bit definitions addr:59 internal referenc es bit definitions these bits control the internal reference mode and internal clk frequency bit bit name default access description 4 standby_mode_on 0 w setting to ?1? sets the as3658 into standby mode. all regulators defined in reg.17h ?reg power1ctrl? and reg.1eh ?reg power2 ctrl are disabled except those regulators enabled by reg.81h ?reg standby mode?. xreset will be pulled to low. a normal startup of all regulators will be done with any interrupt (has to be enabled before entering standby mode). during this startup, regulators defined by reg standby mode register are continuously on. 5 clk_div2 0 r/w divide internal clock oscillator by 2 to reduce quiescent current for low power operation 0 normal mode 1 internal clock frequency divided by two. all timings are increased by two. switching frequency of all dcdc converters are divided by two. reduced transient performance of dcdc converters. table 126. reset control register addr:105 reset control these bits control the power off mode and reset timer bit bit name default access description ams ag technical content still valid table 128. reg standby mode bit definitions addr:129 reg standby mode these bits control the on/off function of the regulators during standby mode bit bit name default access description www.austriamicrosystems.com revision 1v13 122 - 157 as3658 data sheet confidential - detailed description - system functions 6 reg_low_bias_mode 0 r/w 0 normal mode 1 the quiescent current of the following regulators is divided by approx. two: sd1, sd2, sd3, rf1, rf2, rf3. the current capability and performance is also reduce in that mode. (e.g. use this bit only to reduce quiescent current, if syst em and processor is in a low power mode) 0 ldo_rf1_stby_on 0 r/w 0 rf1 ldo is disabled in standby mode 1 rf1 ldo is enabled in standby mode 1 ldo_rf2_stby_on 0 r/w 0 rf2 ldo is disabled in standby mode 1 rf2 ldo is enabled in standby mode 2 ldo_dig1_stby_on 0 r/w 0 dig1 ldo is disabled in standby mode 1 dig1 ldo is enabled in standby mode 3 ldo_dig2_stby_on 0 r/w 0 dig2 ldo is disabled in standby mode 1 dig2 ldo is enabled in standby mode 4 sd1_stby_on 0 r/w 0 step down 1 is disabled in standby mode 1 step down 1 is enabled in standby mode 5 sd2_stby_on 0 r/w 0 step down 2 is disabled in standby mode 1 step down 2 is enabled in standby mode 6 sd3_stby_on 0 r/w 0 step down 3 is disabled in standby mode 1 step down 3 is enabled in standby mode 7 cp_stby_on 0 r/w 0 charge pump is disabled in standby mode 1 charge pump is enabled in standby mode table 127. internal references bit definitions addr:59 internal referenc es bit definitions these bits control the internal reference mode and internal clk frequency bit bit name default access description ams ag technical content still valid table 129. charger supervision addr:14 fuel gauge this bit controls first st artup out of power on reset bit bit name default access description table 130. fuel gauge addr:15 fuel gauge this bit controls first st artup out of power on reset bit bit name default access description www.austriamicrosystems.com revision 1v13 123 - 157 as3658 data sheet confidential - detailed description - system functions 10.2.3 reset cycle during a reset cycle the pin xreset is forced to low for at least res time and all registers are set to their default values (except the registers marked green in the ta b l e 186 on page 148 ). during the reset t i me a normal startup happens (see startup on page 129) , the reset is active until the reset timer (set by register bits r e s_timer<2:0> ) expires. then the voltage on the pin xreset is pulled high by the exte rnal resistor and the whole system is leaving the reset state. 10.2.4 reset control: res_con reset is internally generated from a power supply supervisor and provided to internal logic as well as externally through the open-drain pad xreset. at this point, it could be also forced externally from an external power supply supervisor. additionally reset can be forced by software. 4 auto_shutdown boot rom r/w switch on powe r off mode at first startup(e.g. first battery insertion or first charger insertion) 0 startup of all regulators if battery is inserted, charger insertion, onke y pressed or rtc alarm. 1 startup of all regulators only if onkey is pressed or rtc alarm (no startup on battery insertion; no startup if charger detected, if no_charging=0). xon_enable has to be set in bootrom. if a charger is detected and the bit no_charging=0 (defined by bootrom) and ch_pwroff_en=0 the as3658 will start charging without regulators startup (fully autonomous charging). if the bit no_charging=1 and a charger is detected, the regulator s are started and the charging can be enabled with software control. 5 power_off_at_v_suplow boot rom r/w switch on power off mode if low vsupply is detected during active or standby mode (pin xon= high and bit xon_enable=0) 0 if low battery is detect ed, continuously monitor battery voltage and startup if battery voltage is above resvoltrise 1 if low battery is detected, enter power off mode ams ag technical content still valid www.austriamicrosystems.com revision 1v13 124 - 157 as3658 data sheet confidential - detailed description - system functions 10.3 interrupt controller the interrupt controller generates an interrupt request for the host controller as soon as one or more of the bits in the interrupt 1?3 register is set by pulling low pin xint. all the interrupt sources can be enabled in the interrupt mask 1?3 reg i ster. the interrupt 1?3 registers ar e cleared automatically after the host co ntroller has read them. to prevent the as3658 device from losing an interrupt event, the register that is read is captured before it is transmitted to the host controller via the serial interface. as soon as the transmission of the captured value is complete a logical and operation with the bit wise inverted captur ed value is applied to the register to clear all interrupt bits that have already been transmitted. clearing the read interrupt bits takes 2 cl ock cycles, a read access to the same register before the clearing process has completed will yield a value of ?0?. note that an interrupt that has been present at the previous read access will be cleared as well in case it occurs again before the clearing process has completed. during a read access to one of the interrupt registers th e xint pin will be released . as soon as the transferred bits of the interrupt register have been cleared the xint pin will be pulled low in case a new interrupt has occurred in the meantime. by doing so the interrupt controller will work corr ectly with host controlle rs that are edge- and level-sensitive on their interrupt request input. multiple byte read access is recommended to avoid reading the interrupt 1 register over and over again in response to a new interrupt that ha s occurred in the same register (and thus pulling low pin xint) before the interrupt 2,3 register has been read. table 131. interrupt status 1 register addr:50 interrupt status1 these bits show the status of the interrupts register is reset at power-on-reset and after each read access bit bit name default access description 0 chstate_i na r bit is set when the following status bits are set or reset: trickle, cvm, nobat 1 cheoc_i na r bit is set when the eoc status bits are set or reset: 2 charging_tmax_i na r bit is set when charge timeout ( tricke, cv, cc) has been expired 3 usb_chdet_i na r bit is set when the usb_chdet bit is set or reset. 4 chdet_i na r bit is set when the chdet bit is set or reset. 5 onkey_i na r bit is set when status xon bit is set or reset. 6 ovtmp_i na r bit is set when the lower temperature threshold te m p 110 of the temperature sensor is exceeded for longer than t resmask . 7 lowsup na r bit is set when the main supply voltage vsupply has dropped below v resfall for longer than t resmask . table 132. interrupt status 2 register addr:51 interrupt status2 these bits show the status of the interrupts register is reset at power-on-reset and after each read access bit bit name default access description 0 sd1_lv_i na r bi t is set when voltage of step down1 drops below low voltage threshold (1msec debounce timer) 1 sd2_lv_i na r bit is set when voltage of step down2 drops below low voltage threshold (1msec debounce timer) 2 sd3_lv_i na r bit is set when voltage of step down3 drops below low voltage threshold (1msec debounce timer) ams ag technical content still valid table 133. interrupt status 3 register addr:52 interrupt status3 these bits show the status of the interrupts register is reset at power-on-reset and after each read access bit bit name default access description www.austriamicrosystems.com revision 1v13 125 - 157 as3658 data sheet confidential - detailed description - system functions 3 dig1_lv_i na r bit is set when voltage of ldodig1 drops below low voltage threshold (1msec debounce timer) 4 dig2_lv_i na r bit is set when voltage of ldodig2 drops below low voltage threshold (1msec debounce timer) 5 hphcurr_i na r bit is set when output stage of headphone amplifier exceeds overcurrent limit. 6 bat_temp_i na r bit is set when bit bat_hightemp or bat_lowtemp is set or reset 7 stpup1_i na r bit is set when stpup1_oc or stpup1_det is set. 0 dig3_lv_i na r bit is set when voltage of ldodig3 drops below low voltage threshold (1msec debounce timer) 1 dig4_lv_i na r bit is set when voltage of ldodig4 drops below low voltage threshold (1msec debounce timer) 2 rtc_alarm_i na r bit is set by the rtc, if alarm registers=rtc registers 3 rtc_rep_i na r bit is set by the rtc every second (bit irq_min=0) or minute (bit irq_min=1) 4 mic_con_i na r bit is set if a microphone is detected on mic input 5 mic_rem_i na r bit is set, if the microphone supply is increased (remote key press detected) -> measure mics supply current 6 voxm_i na r bit is set, if voice is detected on mic input 7 tpen_i na r bit is set, if the touchpen pendown is detected table 134. interrupt mask 1 register addr:47 interrupt mask1 these bits mask the interrupt bit bit name default access description 0 chstate_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 1 cheoc_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled table 132. interrupt status 2 register addr:51 interrupt status2 these bits show the status of the interrupts register is reset at power-on-reset and after each read access bit bit name default access description ams ag technical content still valid table 135. interrupt mask 2 register addr:48 interrupt mask2 these bits mask the interrupt bit bit name default access description www.austriamicrosystems.com revision 1v13 126 - 157 as3658 data sheet confidential - detailed description - system functions 2 charging_tmax_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 3 usb_chdet_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 4 chdet_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 5 onkey_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 6 ovtmp_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 7 lowsup_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 0 sd1_lv_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 1 sd2_lv_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 2 sd3_lv_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 3 dig1_lv_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 4 dig2_lv_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 5 hphcurr_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 6 bat_temp_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled 7 stpup1_int_mask 1b r/w 0 interrupt is enabled 1 interrupt is disabled table 134. interrupt mask 1 register addr:47 interrupt mask1 these bits mask the interrupt bit bit name default access description ams ag technical content still valid table 136. interrupt mask 3 register addr:49 interrupt mask3 these bits mask the interrupt bit bit name default access description table 137. low voltage status1 register1 addr:53 low voltage status1 these bits show the low voltage status of the step down and digital regulators bit bit name default access description www.austriamicrosystems.com revision 1v13 127 - 157 as3658 data sheet confidential - detailed description - system functions 0 dig3_lv_int_m 1b r/w 0 interrupt is enabled 1 interrupt is disabled 1 dig4_lv_int_m 1b r/w 0 interrupt is enabled 1 interrupt is disabled 2 rtc_alarm_int_m 1b r/w 0 interrupt is enabled 1 interrupt is disabled 3 rtc_rep_int_m 1b r/w 0 interrupt is enabled 1 interrupt is disabled 4 mic_con_int_m 1b r/w 0 interrupt is enabled 1 interrupt is disabled 5 mic_rem_int_m 1b r/w 0 interrupt is enabled 1 interrupt is disabled 6 voxm_intm 1b r/w 0 interrupt is enabled 1 interrupt is disabled 7 tpen_i_m 1b r/w 0 interrupt is enabled 1 interrupt is disabled 0 sd1_lv na r step down1 low voltage status bit (-10% voltage drop) 1 s d2_lv na r step down2 low voltage status bit (-10% voltage drop) 2 sd3_lv na r step down3 low voltage status bit (-10% voltage drop) 3 dig1_lv na r ldo dig1 low voltage status bit (-50mv voltage drop) 4 dig2_lv na r ldo dig2 low voltage status bit (-50mv voltage drop) 5--- - 6 stpup1_oc na r bit is set by analog part, if overcurrent of dcdc stepup1 occurs for more than 5msec (latched state) 7 stpup1_det na r current detection signal of step up 1 table 138. low voltage status2 register1 addr:54 low voltage status2 these bits show the low voltage status of the step down and digital regulators bit bit name default access description 0 dig3_lv 0b r ldo dig3 low voltage status bit (-50mv voltage drop) 1 d ig4_lv 0b r ldo dig4 low voltage status bit (-50mv voltage drop) ams ag technical content still valid www.austriamicrosystems.com revision 1v13 128 - 157 as3658 data sheet confidential - detailed description - system functions 2 dcdc_curr1_lv 0b r indicates low voltage on dcdc_curr1 3 dcdc_curr2_lv 0b r indicates low voltage on dcdc_curr2 4 dcdc_curr3_lv 0b r indicates low voltage on dcdc_curr3 5 bat_lowtemp 0b r indicates ntc temperature of battery below 0o 6 bat_hightemp 0b r indicates ntc tem perature of batter above 45o (50o) table 138. low voltage status2 register1 addr:54 low voltage status2 these bits show the low voltage status of the step down and digital regulators bit bit name default access description ams ag technical content still valid www.austriamicrosystems.com revision 1v13 129 - 157 as3658 data sheet confidential - detailed description - system functions 10.4 startup figure 56. startup flow chart 10.4.1 normal startup during a normal reset cycle (e.g. after th e battery or a charger is inserted; (see reset generator and xon-key on page 118) ), after v2_5 is above v por and vsupply is above vreset rise a normal startup happens: the external capacitor on cref is charged to 1.8v the 3bit a/d conversion is performed to meas ure the external resistor value rprogram startup state machine reads out the in ternal boot-rom (address defined by boot_ctrl ), start sequence of step- down converter and ldo?s controlled by the boot-rom reset-timer is set by the boot-rom the reset is released when the rese t timer expires (external pin xreset) power on reset xon_enable=0 xon_enable=1 and (chdet=0 or usbchdet=0) no charger detected ? no yes xon pin pulled to gnd no yes batsw_on=0 batsw_mode=0 v bat >v resvolt ? yes no usb sup. detected and chdet=0? no batsw_on=1 batsw_mode=1 switch on battery switch chen=1 usb_chen=1 yes yes startup device v supply >v resvolt ? no yes active state power_off=1 yes batsw_on=0 batsw_mode=0 force_reset=1 no yes trickle switch on switch off batsw_mode batsw_on 0 0 1 1 1 x no v supply www.austriamicrosystems.com revision 1v13 131 - 157 as3658 data sheet confidential - detailed description - system functions 10.4.4 additional startup settings table 141. boot rom bits definitions addr:4 ldo_rf2_voltage these bits defines the startup sequence bit bit name default access description 10.4.5 programmable startup sequences with fuse registers?boot otp its possible to program some startup registers, by using the fuse block: table 142. romf bit definitions addr:196 fuse4 these bits control the startup and are set by factory test bit bit name default access description table 143. romf bit definitions addr:197 addrf0 these bits control the startup and are set by factory test bit bit name default access description table 144. romf bit definitions addr:198 addrf0 these bits control the startup and are set by factory test bit bit name default access description 7 dou ble_ reset rom r/w 0 normal reset pulse 1 apply double reset pulse after the normal rest pulse that is define by res_timer. (pulse on xreset with 2msec high time and 2msec low time 6 slow_startup rom r/w 0 normal startup of ldos defined in boot rom with a separation of 1 milliseconds 1 startup of all ldos defined by boot rom with a time separation of 4 milliseconds 7 romf_en 0 r 0 f usible startup rom disabled 1 feasible startup of rom enabled (uniqueid0.uniqueid10) used for startup 7:0 addrf<7:0> 0 r ea ch bit represents a register address of the bootrom table (0....31) 0 use data of rom table during startup for the according address (0....31) 1 use data of fuse register during startup for the according address, starting with data of register romf0 (up to register romf6 max.) 7:0 addrf<15:8> 0 r ea ch bit represents a register address of the bootrom table (0....31) 0 use data of rom table during startup for the according address (0....31) 1 use data of fuse register during startup for the according address, starting with data of register romf0 (up to register romf6 max.) ams ag technical content still valid table 145. romf bit definitions addr:199 addrf2 these bits control the startup and are set by factory test bit bit name default access description table 146. romf bit definitions addr:200 addrf3 these bits control the startup and are set by factory test bit bit name default access description table 147. romf bit definitions addr:201 romf0 these bits control the startup and are set by factory test bit bit name default access description table 148. romf bit definitions addr:202 romf1 these bits control the startup and are set by factory test bit bit name default access description table 149. romf bit definitions addr:203 romf2 these bits control the startup and are set by factory test bit bit name default access description www.austriamicrosystems.com revision 1v13 132 - 157 as3658 data sheet confidential - detailed description - system functions 7:0 addrf<23:16> 0 r each bit represents a register address of the bootrom table (0....31) 0 use data of rom table during startup for the according address (0....31) 1 use data of fuse register during startup for the according address, starting with data of register romf0 (up to register romf6 max.) 7:0 addrf<31:24> 0 r ea ch bit represents a register address of the bootrom table (0....31) 0 use data of rom table during startup for the according address (0....31) 1 use data of fuse register during startup for the according address, starting with data of register romf0 (up to register romf6 max.) 7:0 romf0 00h r dat a for startup register (used for the first ?1? in the addrf<31:0> register 7:0 romf1 00h r dat a for startup register (used for the second ?1? in the addrf<31:0> register 7:0 romf2 00h r data for startup register (used for the third ?1? in the addrf<31:0> register ams ag technical content still valid table 150. romf bit definitions addr:204 romf3 these bits control the startup and are set by factory test bit bit name default access description table 151. romf bit definitions addr:205 romf4 these bits control the startup and are set by factory test bit bit name default access description table 152. romf bit definitions addr:206 romf5 these bits control the startup and are set by factory test bit bit name default access description table 153. romf bit definitions addr:207 romf6 these bits control the startup and are set by factory test bit bit name default access description www.austriamicrosystems.com revision 1v13 133 - 157 as3658 data sheet confidential - detailed description - system functions 7:0 romf3 00h r data for startup register (used for the fourth ?1? in the addrf<31:0> register 7:0 romf4 00h r data for startup register (used for the fifth ?1? in the addrf<31:0> register 7:0 romf5 00h r dat a for startup register (u sed for the sixth ?1? in the addrf<31:0> register 7:0 romf6 00h r dat a for startup register (used for the seventh ?1? in the addrf<31:0> register ams ag technical content still valid www.austriamicrosystems.com revision 1v13 134 - 157 as3658 data sheet confidential - detailed description - system functions 10.5 protection functions all ldo?s, the dcdc step ups and dcdc step downs have an in tegrated overcurrent protec tion. an overtemperature protection of the chip is also int egrated which can be switched on with the serial interface signal temp_pmc_on (enabled by default; it is not recommended to disable the ov ertemperture protection). the chip has two signals for the serial interface: ov_temp_110 and ov_temp_140. the flag ov_t emp_110 is automatically re set if the overtemperature condition is removed, whereas ov_temp_140 has to be rese t by the serial interface with the signal rst_ov_temp_140. if the flag ov_temp_140 is set, an automatic reset of the co mp lete chip is initiated. the flag ov_temp_140 is not affected by this reset cycle allowing the software to detect the reas on for this unexpected shutdown. table 154. overtem perature detection symbol parameter min typ max unit note table 155. overtermperatur e detection bit definition addr:106 overtemperature control these bits control the startup and are set by factory test bit bit name default access description 10.5.1 temperature supervision a temperature sensor is implemented to provide over-temperature protection of the chip. it generates two flags linked to the two temperature thresholds (110 degrees, 140 d egrees). both thresholds have an hysteresis to prevent oscillation effects. first threshold (110 degrees) sets the flag ov_temp_110, si gn alli ng the serial interface part and software the 110 degrees overtemperature condition. if enabled (ovtmp_int_ma sk=0), an interrupt can be se nd (interrupt ?ovtmp?). thus software can react and can shutdown power co nsuming functions to decrease temperature. the second threshold (140 degrees) initiates a reset cycle a nd set s ov_temp_140: this sets all regulators into power- down mode and stops charging, and performs the reset cycle of the as3658. rst_ov_temp_140 flag in case of overtemperature and an acti vated reset (temp_pmc_on=1 ), the system loses any in formation about the error which activated the reset state. theref ore, a flag is implemented, which indi cates that the reset was caused by overtemperature activation (ov_temp_140 is set). this fl ag is only resetable by writing ?1? to rst_ovtemp_140. t 110 ov_temp_110 rising threshold 95 110 125 oc t 140 ov_temp_140 rising threshold 125 140 155 oc t hyst ov_temp_110 and ov_temp_140 hysteresis 5oc 0 temp_pmc_on 1 r/w sw itch on / off of temperat ure supervision; default: on ? all other bits are only valid if set to ?1? leave at 1 , do not disable 1 ov_temp_110 na r flag that the overtemperature threshold 1 (t 110 ) has been reached 2 ov_temp_140 na r flag that the overtemperature threshold 2 (t 140 ) has been reached ? this flag is not reset by a overtemperature caused rese t and has to be reset by rst_ov_temp_140 3 rst_ov_temp_140 0 w if the overtemperature threshold 2 has been reached, the flag ov_temp_140 is set and a reset cycle is started. ov_temp_140 should be reset by writing 1 and afterward 0 to rst_ov_temp_140 ams ag technical content still valid www.austriamicrosystems.com revision 1v13 135 - 157 as3658 data sheet confidential - detailed description - system functions 10.6 watchdog the purpose of the watchdog is to detect a deadlock of th e software. if the watchdog is active, it must receive a continuous trigger signal within a programmable time window. if there is no signal anymore for a certain time period from a defined pad or special serial interface bit, it starts either a complete reset cycle or changes the state of an output pin, which can be used e.g. as an interrupt to the processor. the watchdog is highly configurable by the following register bits: the complete block can be switched on by wtdg_on = 1 and off by wtdg_on = 0. the watchdog time window is defined by the re gister wtdg_min_timer and wtdg_max_timer. the trigger signal can be configured by register wtdg_trigger and wtdg_gpio_input. (pin curr1-curr4 (gpio1- gpio4) or register bit) if the watchdog expires, the system can start automatically a reset cycle if wtdg_reset_on = 1 table 156. watchdog register definitions addr:60 watchdog control these bits control the watchdog functions bit bit name default access description table 157. watchdog minimum timer definitions addr:61 watchdog_min timer these bits set the watchdog minimum timer bit bit name default access description table 158. watchdog max timer definitions addr:62 watchdog_max timer these bits set the watchdog maximum timer bit bit name default access description any of the general purpose input / outpu t s can be configured to output t he watchdog signal. the watchdog delivers a signal ?wtdg_alarm?, which is normal ?0? and goes to ?1? in the case of a timer-overflow. this signal can be used as e.g. a reset or interrupt for a processor. 0 wtdg_on 0 r/w switches on the comple te watchdog 0 watchdog off 1 watchdog enabled 1 wtdg_res_on 1 r/w if the watchdog expires and wtdg_res_on = 1 a reset cycle will be started 2 wtdg_trigger 0 r/w 0 use the register bit wtdg_sw_signal as trigger signal for the watchdog 1 use one of the gpio pins curr1_gpio1 ? curr4_gpio4 as trigger input for the watchdog; the actual pin is selected by setting gpioxiosf to 01b(watchdog mode) and gpioxmode=010b (gpio digital input) (x=1...4) 7:0 wtdg_min_timer 00h r/w d efi nes the minimum watchdog trigger time (lsb=7.5ms, range: 0 ? 1.9s) 7:0 wtdg_max_timer ffh r/w defines the maximum watchdog trigger time (lsb=7.5ms, range: 7.5ms ? 1.9s), do not set to (00)h ams ag technical content still valid table 159. watchdog software signal definitions addr:63 watchdog software signal this bit sets the watchdog software trigger bit bit name default access description www.austriamicrosystems.com revision 1v13 136 - 157 as3658 data sheet confidential - detailed description - system functions figure 57. watchdog timing diagram 10.7 general purpose 10 bit adc table 160. adc characteristics symbol parameter min typ max unit note 0 wtdg_sw_signal 0 r/w trigger input by the serial interface if wt dg_trigg er = 0 resolution 10 bit in put v oltage range vin 0 1.8 v differential nonlinearity dnl 0.25 lsb 1lsb 1.76mv (depending on selected channel) integral nonlinearity inl 0.5 lsb input offset voltage vos 2 lsb input impedance rin 100 m input capacitance cin 9 pf power supply current idd 500 a during conversion only power down current idd 100 na transient pa rameters (25c) conversion time tc 40 s clock frequency fc f clk_int / 8 khz internal clk frequency/8 programmable: 0.2 to 0.2875 mhz settling time of s&h ts 1 s adc_in1 pull up current 14.25 15 15.75 a pull up current for adc_in1, if adc_idc=1111b t min t max t min t max wtdg_trigger ams ag technical content still valid table 161. adc control registers bits addr:96 adc_control this register controls the 10 bit adc bit bit name default access description table 162. adc msb result register addr:97 adc_msb result this register shows the msb result of the adc conversion bit bit name default access description www.austriamicrosystems.com revision 1v13 137 - 157 as3658 data sheet confidential - detailed description - system functions 3:0 adc_select 0000b r/w selects an adc channel 0000 adc1_in (lsb = 1.76mv) 0001 adc2_in (lsb = 1.76mv) 0010 v bat battery voltage (lsb=5.27mv) 0011 vcharger (lsb=17. 6mv) clamping at 10v 0100 v_usb voltage (lsb=5.27mv) 0101 not used 0110 temperature sensor: die temperature [c] = adc_result * 0.866 ? 274 0111 adc test channel ? do not use 1000 check voltage on mics for remote control or external voltage measurement (lsb=3.52mv) 1001 vback voltage (lsb=3.52mv) 4 adc_slow 0b r/w select adc sampling frequency 0 275khz (conversion time: 60s) 1 70khz (conversion time: 240s) 5 - - - reserved (do not use) 6 adc_on 0b r/w writing a 1 into this bit continuously activates the adc s/h and the input multiplexer. the adc and the mux are also activated for a conversion period when start_conversion is set to ?1? ? useful for high impedance input sources on adc1_in or adc2_in 7 start_conversion 0b r/w writing a 1 into this bit starts one adc conversion. 0 d3 na r adc result register 1 d 4 na r adc result register 2 d5 na r adc result register 3 d6 na r adc result register 4 d7 na r adc result register 5 d8 na r adc result register 6 d9 na r adc result register 7 result_not_ready na r indicates end of conversion 0 result is ready 1 conversion is running ams ag technical content still valid table 163. adc lsb result register addr:98 adc_lsb result this register shows the lsb result of the adc conversion bit bit name default access description table 164. adc idac register addr:46 adc idac this register controls the current sink on pin adc_in1 bit bit name default access description www.austriamicrosystems.com revision 1v13 138 - 157 as3658 data sheet confidential - detailed description - system functions figure 58. adc timing-diagram 0 d0 na r adc result register 1 d1 na r adc result register 2 d2 na r adc result register 7:3 - - - reserved (do not use) 0 adc_idac 000b r/w curre nt sou rce at adc_in1 input set to 0000 if battery temperature supervision is enabled. 0000 0a (current sink disabled) 0001 1a ... 1111 15 a i2c bus adc_on sample 275khz start_conversion=1 result_not ready d<9:0> old_data data not valid data ready start_adc 123 1213 ams ag technical content still valid www.austriamicrosystems.com revision 1v13 139 - 157 as3658 data sheet confidential - detailed description - system functions 10.8 internal references (v, i, f clk ) the internal reference circuits needs the following external components: table 165. reference external components symbol parameter min typ max unit note table 166. references parameters symbol parameter min typ max unit note to reduce the current consumption of the chip, the circui t can be set into a special low power mode with the serial interface bit ? low_power_on? . all specification parameters except the nois e parameters are still valid for this mode. table 167. internal references bit definitions addr:59 internal referenc es bit definitions these bits control the internal reference mode and internal clk frequency bit bit name default access description 10.8.1 low power mode use bit low_power_on (reg. references control (see table 167)) to activate the low power mode. in this mode the on-chip voltage reference and the temperature supervision co mp arators are operating in pulsed mode. this reduces the quiescent current of the as3658 by 45ua (typ.). because of the pulsed function some sp ecifications are not fulfilled in this mode (e.g. increased noise), but still the full functionality is available. note: low p ower mode can be controlled by the serial interface. c ext external filter capacitor -10% 100 +10% nf ceramic low-esr capacitor between cref and vss r bias external bias current set resistor -1% 220 +1% k bias current set resistor between rbias and vss v cext reference voltage -1% 1.8 +1% v low noise trimmed voltage reference ? connected to pad cref; do not load f clk accuracy of internal reference clock -10 f clk +10 % adjustable by serial interface register clk_int 0 low_power_on 0b r/w 0 s tandard mode 1 low power mode ? all specification except noise parameters are still valid 3:1 clk_int 110b r/w sets the internal clk frequency f clk used for fuel gauge, dcdcs, pwm, charge pump. all frequencies, timings and delays in this datasheet are based on 2.2mhz clk_int 000b 1.6 mhz 001b 1.7 mhz 010b 1.8 mhz 011b 1.9 mhz 100b 2.0 mhz 101b 2.1 mhz 110b 2.2 mhz (default) 111b 2.3 mhz ams ag technical content still valid www.austriamicrosystems.com revision 1v13 140 - 157 as3658 data sheet confidential - detailed description - system functions 10.9 real-time clock (rtc) module the rtc module provides time information to the system. it is implemented as a 6-bit counter that is incremented every second - with the 32khz oscillator delivering the necessary accurate time base ? and is reset to 0 each time the counter value is 60. an additional 24-bit minute counter is incriminated each time the 6-bit counter is reset to 0. both counters are set to 0 at a power-on-reset. the host controll er can set the counter to any value by setting the rtc 1?4 registers. to prevent ambiguous time informatio n becau se of the 30-bit value being incr emented before all of the 4 registers have been read or written, a 30-bit parallel shadow register is implemented. every time a write/read access via the serial interface occurs the parallel shadow register is upda ted with the current value of the 30-bit counter. any write access to the rtc 1 register will disable the update of the para llel register and set the value of the appropriate byte of the parallel register. any subsequent write access to the rtc 4 register will transfer the current value of the 30-bit parallel register to the rtc 1?4 register s and the update of the parallel register is enabled again. similarly, any read access to the rtc 1 register will freeze the current value of the parallel register a nd submit the appropriate byte to the host controller via the serial interfac e. any subsequent read access to the rtc 4 register will enable the update of the parallel register again. this mechanism ma kes sure that the maximum error of the va lue that is written to or read from the registers is 1 second. the startup state after power on reset:rtcsecond= 3f , rtcminute1=ff, rtcminute2=ff, rtcminute3=ff to start the rtc, rtc_mode bits have to be set to a non ze ro value, and the rtc registers have to be set. the rtc stops automatically at its highest value (3f,ff,ff,ff) to prevent overrun. table 168. rtc second register addr:64 rtcsecond these bits represents the actual rtc second register register is reset at power-on-reset only bit bit name default access description table 169. rtc minute1 register addr:65 rtcminute1 these bits represents the actual rtc minute1 register register is reset at power-on-reset only bit bit name default access description table 170. rtc minute2 register addr:66 rtcminute2 these bits represents the actual rtc minute2 register register is reset at power-on-reset only bit bit name default access description table 171. rtc minute3 register addr:67 rtcminute3 these bits represents the actual rtc minute3 register register is reset at power-on-reset only bit bit name default access description 5:0 rtcsecond 00h r/w bits 5:0 of the 6-bit rtc second counter 7:6 - - reserved 7:0 rtcminute1 00h r/w bits 7?0 of th e 24-bit rtc minute counter 7:0 rtcminute2 00h r/w bits 15:8 of the 24-bit rtc minute counter 7:0 rtcminute3 00h r/w bits 23:16 of th e 24-bi t rtc minute counter ams ag technical content still valid www.austriamicrosystems.com revision 1v13 141 - 157 as3658 data sheet confidential - detailed description - system functions the rtc module includes an alarm function. when the cont ent of the rtc 1?4 register s equals the content of the rtc alarm 1?4 registers bit rtcalarm will be set in the interrupt 1 register. furthermore the rtc module can generate an interrupt every second (rtc1sec will be set) and every minute (rtc1min will be set every time the 6-bit second counter is reset to 0). for further details on interrupt generation please refer to interrupt controller on page 124 . to avoid ambiguous behavior during write access to the rt c alarm 1 ?4 registers any write access to the rtc alarm 1 register will disable the alarm function; any subsequent write access to the rtc alarm 4 will enable the alarm function again. table 172. rtc alarm second register addr:68 rtc alarmsecond these bits set the rtc alarm seconds register is reset at power-on-reset only bit bit name default access description table 173. rtc alarm minute1 register addr:69 rtc alarmminute1 these bits set the rtc alarm minute1 register is reset at power-on-reset only bit bit name default access description table 174. rtc alarm minute2 register addr:70 rtc alarmminute2 these bits set the rtc alarm minute2 register is reset at power-on-reset only bit bit name default access description table 175. rtc alarm minute3register addr:71 rtc alarmminute3 these bits set the rtc alarm minute3 register is reset at power-on-reset only bit bit name default access description 5:0 rtcalarmsecond 3fh r/w bits 5?0 of 6-bit rtc second alarm value 7:0 rtcalarmminute1 ffh bits 7:0 of t he 24 -bit rtc minute alarm value 7:0 rtcalarmminute2 ffh bits 15:8 of the 24-bit r tc minute alarm value 7:0 rtcalarmminute3 ffh bits 23:16 of the 24-bit rtc minute alarm value ams ag technical content still valid table 176. rtct register addr:72 rtct these bits set the rtc correction and rtc interrupt mode register is reset at power-on-reset only bit bit name default access description table 177. reset timer register addr:22 reset timer these bits set rtc modes bit bit name default access description www.austriamicrosystems.com revision 1v13 142 - 157 as3658 data sheet confidential - detailed description - system functions 6:0 rtc_tbc<6:0> 0000000 r/w these bits are used to correct the inaccuracy of the used 32khz crystal. correction is done all 8 seconds by removing or adding two clock cycles. trimming register for rtc, 128 steps @ 7.6ppm 100000 - 480.4ppm 100001 -472.8ppm 111111 -7.6ppm 000000 0ppm(default) 000001 7.6ppm 011110 472.8ppm 011111 480.4ppm 7 rtc_irq_mode 0 r/w 0 generate an interrupt every second 1 generate an interrupt every minute the interrupt has to be enabled by rtc_rep_int_m=0 4 rtc_alarm_wakeup_en rom r/w 0 disabl es rtc alarm wakeup in power off mode 1 enable rtc alarm wakeup in power off mode 5 rtc_rep_wakeup_en rom r/w 0 disables rtc repeated wakeup in power off mode 1 enable rtc repeated wakeup in power off mode 7:6 rtc_mode rom r/w 00 32khz oscillator off 01 32khz oscillator enabled 10 32khz oscillator enabled, pin q32k enabled 11 reserved (do not use) ams ag technical content still valid www.austriamicrosystems.com revision 1v13 143 - 157 as3658 data sheet confidential - detailed description - system functions 10.10 touchpen interface the touchpen interface controls a resistiv e touchpen. it has the following features: low power pen detect measure pen x,y position measure pen pressure (z-position) interrupt, if x,y,z data is available; one dedicated ou tput ? curr4_gpio4 can be configured to be used as touchpen interrupt output and/or standard interrupt output xint the conversion interval can be adjusted up to 16 adc conversion can be averaged internally the sample time of the adc can be adjusted the pin curr3_gpio3 can be configured to enable/disable the adc conversion (useful if the processor updates the lcd to avoid parallel reading of the touchpen position) the touchpen interface shares the pins with the spdif output and the i2s output 3. if the touchpen interface is used, the spdif and the i2s output 3 cannot be used (and has to be disabled). note: th e touchpen interface and the ?general purpose 10 bit adc? can be used at the same time. figure 59. touchpen block diagram ;< ; !"#$%" " " " &&&"" '( !) $ *+&*,-$. , % "$ $ ,"* + $&,-&$ *+&*,-$. , % "$ $ ,"* + / 0" & "1, 0"2% 3 $$$$ ,$) $$$$) '4 ### "*%+ ' '5 ' !" )-& *6 *-6 '('7'8$"*%+" 0* 1 6,"& ' 6,"& 0* 1 6,"& ' 6,"& ' 6,"& 3%" 9:; < 3+" 9; < =%" 9:; < =+" 9; < %" 9:; < +" 9; < 9 ; < 3%" &* $"*& ,% > ? > 6, 1*, $>@ a * $> a * ,-$0,60$ &,6 1&,,6$$ ,"+*= / 0" & &.* ,6,*+ &+ >( ?( > 6, , * $ 0" & ,&.* $,&& && 6, / & ""&$,&& $>(@ a $ b6b$ $&$ * $>( a .&%$ ams ag technical content still valid www.austriamicrosystems.com revision 1v13 144 - 157 as3658 data sheet confidential - detailed description - system functions the touchpen controller is operating ac cording to the following state diagram: figure 60. touchpen state diagram 10.10.1 software guidelines 1. setup the configuration registers (t pen ? control 1..3) according the hardware 2. enable receiving of touchpen interrupt s (either th rough xint or gpio4_curr4) 3. upon receiving of a touchpen interrupt, readout tpen_x msb, tp en_ymsb (and if required tpen_pressmsb and tpen_xypresslsb) with a single i2c blockread . this ensured, that the x,y,z is correctly reado ut and all data belong to one single touchpen x,y,z conversion 4. perform all the required proce ssing with the data (e.g. accept a pen-dow n only if the pen is forced onto the touchscreen with a minimum pressure [z-position]) !"#"$%#&#&" ' (& ) ) (& (" *+, *+, *+, (" (&- . ams ag technical content still valid www.austriamicrosystems.com revision 1v13 145 - 157 as3658 data sheet confidential - detailed description - system functions 10.10.2 touchpen registers table 178. touchpen register map register definition addr default content name b7 b6 b5 b4 b3 b2 b1 b0 note: the cells marked in color are read only table 179. touchpannel result register bits addr:108 touchpad_xmsb result x-msb result register bit bit name default access description table 180. touchpannel result register bits addr:109 touchpad_ymsb result y-msb result register bit bit name default access description table 181. touchpannel result register bits addr:110 touchpad_pressure result pressure result register bit bit name default access description table 182. touchpannel result register bits addr:111 touchpad_xy - lsb result x - msb result register bit bit name default access description tpen_xmsb 108 na xd9 xd8 xd7 xd6 xd5 xd4 xd3 xd2 tpen_ymsb 109 na yd9 yd8 yd7 yd6 yd5 yd4 yd3 yd2 tpen_pressmsb 110 na pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 tpen_xypresslsb 111 na pd1 pd0 0 yd1 yd0 0 xd1 xd0 tpen ? control 1 112 00h tpen_st_ pen tpen_eo c tpen_avg tpen_soc tpen_convint tpen_on tpen ? control 2 113 00h tpen_so cpd tpen_wa it tpen_curr press tpen_pu tpen ? control 3 114 00h tpen_timeo ut _en tpen_deb ounce tpen_sample 7:0 tpen_xmsb 00000000 r x ? msb data 7:0 tpen_ymsb 00000000 r y ? msb data 7:0 tpen_pressmsb 00000000 r pressure - data 1:0 tpen_xlsb 00 r x ? lsb data 4 : 3 tpen_ylsb 00 r y ? lsb data 7:6 tpen_presslsb 00 r pressure ? lsb data ams ag technical content still valid table 183. touchpannel control register bits addr:112 touchpad ? control 1 this register controls the different modes of the touchpad bit bit name default access description www.austriamicrosystems.com revision 1v13 146 - 157 as3658 data sheet confidential - detailed description - system functions 0 tpen_on 0 r/w enables touch pen function 0 off (no wakeup on pen down) 1 pen detect enabled wakes up pen digitizer check pen_status -> if pen- detect or tpen_soc_pd=1 and tpen_soc=1 then perform x,y,z measurements 2:1 tpen_convint 00 r/w conversion interval timer 00 no delay between conversions 01 every 512 clock periods (0,5 ms) adc ? averaging limited to max. 4 10 every 1024 clock periods (1ms) adc ? averaging limited to max. 8 11 every 10240 clock periods (10ms) 3 tpen_soc 0 r/w start conversion (x,y, and z conversion) 0 no conversion if pen down detected 1 start conversion if pen down detected or tpen_soc_pd=1 and tpen_on=1 (x, y and z-pressure measurement) 5:4 tpen_avg 0 r/w averaging of x and y measurement 00 no averaging 01 4 measurements (per channel) 10 8 measurements (per channel) 11 16 measurements (per channel) 6 tpen_eoc 0 r/w adc - end of conversion bit 0 tp in power down or conversion ongoing 1 valid tp data available (x,y, and pressure) generates an interrupt on gpio4_curr4 and/or xint; the interrupt is released when the readout from the tpen_xmsb is started 7 tpen_st_pen 0 r pen status 0 penup 1 pendown ams ag technical content still valid table 184. touchpannel control register bits addr:113 touchpad ? control 2 this register controls the different modes of the touchpad bit bit name default access description table 185. touchpannel control register bits addr:114 touchpad ? control 3 this register controls the different modes of the touchpad bit bit name default access description www.austriamicrosystems.com revision 1v13 147 - 157 as3658 data sheet confidential - detailed description - system functions 4:0 tpen_pu 00000 r/w internal resistor used for pen detection 00000 do not use this setting 00001 4k 00010 8k ... 00100 16k ... 01000 32k ... 10000 64k (most sensitive) ... 11111 ~ 2k 5 tpen_currpress 0 r/w current used for pressure measurement 0 200a 1 400a 6 tpen_wait 0 r/w 0 do not wait until tpen_xmsb is readout 1 start next adc ? conversion after data is read from register tpen_xmsb 7 tpen_soc_pd 0 r/w 0 start conversion only if tpen_st_pen is 1 and tpen_soc=1 and tpen_on=1 1 measure regardless of pen status (only if tpen_soc=1 and tpen_on=1) 0:1 tpen_sample 00 r/w sample t i me of adc 0 3s 11 0 s 25 0 s 3 200s 2 tpen_debounce 0 r/w 0 pen-down debounce time 100s 1 pen-down debounce time = 3ms 3 tpen_timeout _en 0 r/w enables timeout signal (adc conversion is stopped during tiemeout = 1) 0o f f 1 gpio3_curr3 can be configured as input for the timeout signal ? see block diagram ams ag technical content still valid www.austriamicrosystems.com revision 1v13 148 - 157 as3658 data sheet confidential - register map 11 register map table 186. register map register definition addr hex default content name b7 b6 b5 b4 b3 b2 b1 b0 step down voltage1 00hrom sd1_clki nv sd1_freq u step_down1_v step down voltage2 11hrom sd2_clki nv sd2_freq u step_down2_v step down voltage3 22hrom sd3_clki nv sd3_freq u step_down3_v ldo_rf1 voltage 33hrom rf1_swpr ot_en rf1_lcurr _en ldo_rf1_v ldo_rf2 voltage 44hrom double_r eset slow_sta rtup rf2_lcurr _en ldo_rf2_v ldo_rf3 voltage 55hrom rf3_hotpl ug_en rf3_lcurr _en ldo_rf3_v ldo_dig1 voltage 6 6h rom ldo_dig1_v ldo_dig2 voltage 7 7h rom ldo_dig2_v ldo_dig3 voltage 8 8h rom ldo_dig3_v ldo_dig4 voltage 9 9h rom ldo_dig4_v usb charger control 10 ah rom ext_bats w_en no_char ging dis_bats w_temp _prot usb_chg en usb_current charger control1 11 bh rom isolate_b at ch_det_ 500ms charging _tmax usb_hol d_chdet auto resume chovd eten ch_pwr off_en chen battery voltage monitor 12 ch rom fastres en supres en resvoltfall resvoltrise charger config 13 dh rom chvoltresume vsupply_min chvolteoc charg er supervision 14 eh rom ntc_type ntc_hyst ntc_high _temp auto_sh utdown ch_timeout fuelgauge 15 fh rom ntc_on power_o ff_at_vs uplow calmod calreq updreq fgen charger current 16 10h rom ch_voltage constantcurrent tricklecurrent charge pump control 17 11h rom sdx_1a_mode sd1_dvm_time cp_freq cp_puls eskip gpio 1 18 12h rom gpio1_pulls gpio1_in vert gpio1_iosf gpio1_mode gpio 2 19 13h rom gpio2_pulls gpio2_in vert gpio2_iosf gpio2_mode gpio 3 20 14h rom gpio3_pulls gpio3_in vert gpio3_iosf gpio3_mode gpio 4 21 15h rom gpio4_pulls gpio4_in vert gpio4_iosf gpio4_mode ams ag technical content still valid www.austriamicrosystems.com revision 1v13 149 - 157 as3658 data sheet confidential - register map reset timer 22 16h rom rtc_mode rtc_rep_ wakeup _en rtc_alar m_wake up_en xon_ena ble res_timer reg power1 ctrl @ 6 msec 23 17h rom cp_on sd3_on sd2_on sd1_on ldo_dig2 _on ldo_dig1 _on ldo_rf2_ on ldo_rf1_ on reg power1 ctrl @ 7 msec 24 18h rom cp_on @ 7 msec sd3_on @ 7 msec sd2_on @ 7 msec sd1_on @ 7 msec ldo_dig2 _on @ 7 msec ldo_dig1 _on @ 7 msec ldo_rf2_ on @ 7 msec ldo_rf1_ on @ 7 msec reg power1 ctrl @ 8 msec 25 19h rom cp_on @ 8 msec sd3_on @ 8 msec sd2_on @ 8 msec sd1_on @ 8 msec ldo_dig2 _on @ 8 msec ldo_dig1 _on @ 8 msec ldo_rf2_ on @ 8 msec ldo_rf1_ on @ 8 msec reg power1 ctrl @ 9 msec 26 1ah rom cp_on @ 9 msec sd3_on @ 9 msec sd2_on @ 9 msec sd1_on @ 9 msec ldo_dig2 _on @ 9 msec ldo _dig1 _on @ 9 msec ldo_rf2_ on @ 9 msec ldo_rf1_ on @ 9 msec reg power1 ctrl @ 10 msec 27 1bh rom cp_on @10 msec sd3_on @ 10 msec sd2_on @ 10 msec sd1_on @ 10 msec ldo_dig2 _on @ 10 msec ldo_dig1 _on @10 msec ldo_rf2_ on @10 msec ldo_rf1_ on @ 10 msec reg power1 ctrl @ 11 msec 28 1ch rom cp_on @ 11 msec sd3_on @11 msec sd2_on @ 11 msec sd1_on @ 11 msec ldo_dig2 _on @ 11 msec ldo_dig1 _on @ 11 msec ldo_rf2_ on @ 11 msec ldo_rf1_ on @ 11 msec reg power1 ctrl @ 12 msec 29 1dh rom cp_on @ 12 msec sd3_on @ 12 msec sd2_on @ 12 msec sd1_on @ 12 msec ldo_dig2 _on @ 12 msec ldo_dig1 _on @ 12 msec ldo_rf2_ on @ 12 msec ld o_rf1_ on @ 12 msec reg power2 ctrl 30 1eh rom rf3_sw stpup2_ on stpup1_ on rf2_sw rf1_sw ldo_dig4 _on ldo_dig3 _on ldo_rf3 reg gpio ctrl 31 1fh rom ldo_dig3 _gpio sd3_gpi o sd2_gpi o sd1_gpi o ldo_dig2 _gpio ldo_dig1 _gpio ldo_rf2_ gpio ldo_rf1_ gpio step up dc/dc control 32 20h 00h stpup2_r es stpup2_f req stpup2_f b_auto stpup1_r es stpup1_f req stpup2_ clkinv step up1 dc/ dc control 33 21h 00h stpup1_o c_timeou t stpup1_ shortprot stpup1_ clkinv stpup1_v step up2 dc/ dc control 34 22h 00h stpup2_p rot stpup2_fb stpup2_v step down control1 35 23h 00h sd2_nsw _on sd2_psw _on sd1_nsw _on sd1_psw _on step down control2 36 24h 00h sd3_dis_ pon sd2_dis _pon sd1_dis _pon sdx_lpo sd3_nsw _on sd3_psw _on step down charger control 37 25h 02h sd3_dis _curmin sd2_dis _curmin sd1_dis _curmin sdc_pas s_ mode sdc_pon sdc_freq u backup battery charger 38 26h 40h bbcpwr save bbcvolt bbccur bbcres off bbcmode dcdc_curr1 value 39 27h 00h dcdc_curr1_current table 186. register map register definition addr hex default content name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid www.austriamicrosystems.com revision 1v13 150 - 157 as3658 data sheet confidential - register map dcdc_curr2 value 40 28h 00h dcdc_curr2_current curr1 value 41 29h 00h curr1_current curr2 value 42 2ah 00h curr2_current curr3 value 43 2bh 00h curr3_current curr4 value 44 2ch 00h curr4_current dcdc_curr3 value 45 2dh 00h dcdc_curr3_current adc idac 46 2eh 00h adc_idac interrupt mask1 47 2fh ffh lowbat_i nt_m ovtmp_ int_m onkey_ int_m chdet_ int_m usb_chd et_ int_m charging _tmax_i nt_m cheoc_i nt_m chstate_ int_m interrupt mask2 48 30h ffh stpup1_i nt_m bat_tem p_m hphcurr_ int_m dig2_lv_i nt_m dig1_lv_i nt_m sd3_lv_i nt_m sd2_lv_i nt_m sd1_lv_i nt_m interrupt mask3 49 31h ffh - voxm_in t_m mic_rem _int_m mic_con _int_m rtc_rep_i nt_m rtc_alar m_int_m dig4_lv_i nt_m dig3_lv_i nt_m interrupt status1 50 32h na lowbat_i ovtmp_i onkey_i chdet_i usb_chd et_i charging _tmax_i cheoc_i chstate_ i interrupt status2 51 33h na stpup1_i bat_tem p_i hphcurr_ i dig2_lv_i dig1_lv_i sd3_lv_i sd2_lv_i sd1_lv_i interrupt status3 52 34h na - voxm_i mic_rem _i mic_con _i rtc_rep_i rtc_alar m_i dig4_lv_i dig3_lv_i low voltage status1 53 35h na stpup1_d et stpup1_ oc dig2_lv dig1_lv sd3_lv sd2_lv sd1_lv low voltage status2 54 36h na bat_high temp bat_lowt emp dcdc_cu rr3_lv dcdc_cu rr2_lv dcdc_cu rr1_lv dig4_lv dig3_lv gpio signal 55 37h na gpio4_in gpio3_in gpio2_in gpio1_in gpio4 gpio3 gpio2 gpio1 pwm frequency control high time 56 38h 00h pwm_h_time pwm frequency control low time 57 39h 00h pwm_l_time curr control 58 3ah 00h pwm_div dcdc_curr3_ctrl dcdc_curr2_ctrl dcdc_curr1_ctrl references control 59 3bh 0ch reg_low _bias_m ode clk_div2 standby _mode_ on clk_int low_pow er_on watchdog control 60 3ch 02h wtdg_tri gger wtdg_re s_on wtdg_on watchdog_min timer 61 3dh 00h wtdg_min_timer watchdog_max timer 62 3eh ffh wtdg_max_timer watchdog software signal 63 3fh 00h wtdg_ sw_sig table 186. register map register definition addr hex default content name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid www.austriamicrosystems.com revision 1v13 151 - 157 as3658 data sheet confidential - register map rtcsecond 64 40h 00h second<7:0> rtcminute1 65 41h 00h minute<7:0> rtcminute2 66 42h 00h minute<15:8> rtcminute3 67 43h 00h minute<23:16> rtcalarmseco nd 68 44h 3fh alarmsecond<7:0> rtcalarmminu te1 69 45h ffh alarmminute<7:0> rtcalarmminu te2 70 46h ffh alarmminute<15:8> rtcalarmminu te3 71 47h ffh alarmminute<23:16> rtct 72 48h 00h rtc_irq_ mode rtc_tbc<6:0> sram 73 49h 00h sram<7:0> audio set1 74 4ah 00h equ_on mclk256 mclk_inv ert aud_ldo _on gnd_sw _on mix_on dac_on lin_on audio set2 75 4bh 00h i2s_mclk _en i2s_sele ct ibr_hph i2s_3_o n dith_on ibr_dac audio set3 76 4ch 00h linmix_of f micmix_ off dacmix_ off agc_off mic_on voxm_o n hp_pulld _en pll_mod e dac_l 77 4dh 00h dac_mut e_off dal_vol dac_r 78 4eh 00h dar_vol adc_l 79 4fh 00h ad_fs2 adc_mut _off adc_on adl_vol adc_r 80 50h 00h adcmux adc2dac adr_vol hph out r 81 51h 00h hp_ovc_to hpcm_of f hpr_vol hph out l 82 52h 00h hp_mute hp_on hp_mux hpl_vol line out r 83 53h 00h ibr_line liner_vol line out l 84 54h 00h line_mut e line_on dac2line _on linel_vol line_in_r 85 55h 00h mute_mi c_sf mute_off _inr lir_vol line_in_l 86 56h 00h mute_off _inl lil_vol mic_r 87 57h 00h mic_agc _off pre_gain mr_vol mic_l 88 58h 00h msup_off mute_off _d rdet_off ml_vol spdif 89 59h 00h audio_off sclk_inv ert sdo3_se lect spdif_co py_ok spdif_m clk_inv spdif_inv alid spdif_cntr eq_lp 90 5ah 00h eq_lp_gain table 186. register map register definition addr hex default content name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid www.austriamicrosystems.com revision 1v13 152 - 157 as3658 data sheet confidential - register map eq_band1 91 5bh 00h eq_band1_gain eq_band2 92 5ch 00h eq_band2_gain eq_band3 93 5dh 00h eq_band3_gain eq_hp 94 5eh 00h eq_hp_gain eq_preamp 95 5fh 00h eq_ pre_gain adc_control 96 60h 00h start_con version adc_on adc_slo w adc_select adc_msb result 97 61h na result_no t_ready d9 d8 d7 d6 d5 d4 d3 adc_lsb result 98 62h na d2 d1 d0 chargerstatus 99 63h na chlinear nobat eoc cvm trickle resume chact chdet chargerstatus_ usb 100 64h na ch_over voltage batsw_o n batsw_ mode usb_ch act usb_ch det deltacharge ms b 101 65h na sign 2 14 2 13 2 12 2 11 2 10 2 9 2 8 deltacharge ls b 102 66h na 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 elapsedtime m sb 103 67h na 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 elapsedtime ls b 104 68h na 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 reset control 105 69h na onkey_r eset_5s reset_reason xon_inp ut power_o ff force_re set overtemperatu re control 106 6ah na rst_ov_t emp_14 0 ov_temp _140 ov_temp _110 temp_p mc_on boot_status 107 6bh na rom_ valid rom_adr tpen_xmsb 108 6ch na xd9 xd8 xd7 xd6 xd5 xd4 xd3 xd2 tpen_ymsb 109 6dh na yd9 yd8 yd7 yd6 yd5 yd4 yd3 yd2 tpen_pressmsb 110 6eh na pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 tpen_xypressls b 111 6fh na pd1 pd0 0 yd1 yd0 0 xd1 xd0 tpen ? control 1 112 70h 00h tpen_st_ pen tpen_eo c tpen_avg tpen_so c tpen_convint tpen_on tpen ? control 2 113 71h 00h tpen_soc pd tpen_wa it tpen_cur rpress tpen_pu tpen ? control 3 114 72h 00h tpen_tim eout_en tpen_de bounce tpen_sample asic id 1 127 7fh na 1 1 0 0 1 1 0 1 asic id 2 128 80h na 0 1 0 1 rev reg_ standby mod 129 81h 00h cp_stby_ on sd3_stb y_on sd2_stb y_on sd1_stb y_on ldo_dig2 _stby_o n ldo_dig1 _stby_o n ldo_rf2_ stby_on ldo_rf1_ stby_on table 186. register map register definition addr hex default content name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid www.austriamicrosystems.com revision 1v13 153 - 157 as3658 data sheet confidential - register map usb_current_tri m 130 82h 00 usb_add_trim_current<2:0> i2s master control1 131 83h 00 i2s_clk_divider<7:0> i2s master control2 132 84h 00 pcm_mo de sdo_on_ mclk1_e n i2s_mclk _out_en i2s_lrclk _sclk_ou t_en i2s_mas ter_on i2s_clk_divider<10:8> step down control3 133 85h 00 sd3_uvli mit sd2_uvli mit sd1_uvli mit uniqueid0, addrf0 197 c5h na id<7:0>, addrf<7:0> uniqueid1, addrf1 198 c6h na id<15:8>, addrf<15:8> uniqueid2, addrf2 199 c7h na id<23:16>, addrf<23:16> uniqueid3, addrf3 200 c8h na id<31:24>, addrf<31:24> uniqueid4, romf0 201 c9h na id<39:32>, romf0 uniqueid5, romf1 202 cah na id<47:40>, romf1 uniqueid6, romf2 203 cbh na id<55:48>, romf2 uniqueid7, romf3 204 cc h na id<63:56>, romf3 uniqueid8, romf4 205 cd h na id<71:64>, romf4 uniqueid9, romf5 206 ceh na id<79:72>, romf5 uniqueid10, romf6 207 cfh na id<87:80>, romf6 entries marked are read only entries are not reset in power off mode table 186. register map register definition addr hex default content name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid www.austriamicrosystems.com revision 1v13 154 - 157 as3658 data sheet confidential - package drawings and marking 12 package drawings and marking figure 61. ctbga124 8x8 0.5mm pitch 0. top view bottom view (124 solder balls ) side view dimension & tolerance asme y14.5m unit : mm customer : ams company sheet ase korea 1 of 2 ase package outline advanced semiconductor engineering korea, inc. date issue dwg no. oct.010, 2007 97spp01046a o note 1. general tolerance : 0.10 title : pod for fbga 8mm x 8mm x 1.09mm, 2l, 0.65cap, 124bga, 0.50pitch, 0.30ball ams ag technical content still valid www.austriamicrosystems.com revision 1v13 155 - 157 as3658 data sheet confidential - package drawings and marking figure 62. ctbga124 marking 12.1 pinout drawing (t op view) ctbga 8x8mm figure 63. pinout drawing table 187. package code aywwzzz a y ww zzz b ... for green year working week assembly / packaging free choice table 188. boot rom revison x b, c, d, e, e1 or f bottom view (ball side) 14 a b c d c e f g h j k l m n p 13 12 11 10 9 8 7 6 5 4 3 2 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p c inner balls pcb layout example shown with dotted blue lines ams ag technical content still valid www.austriamicrosystems.com revision 1v13 156 - 157 as3658 data sheet confidential - ordering information 13 ordering information the device is available as the standard products listed in table 189 . table 189. ordering information model marking descriptiom delivery form package as3658b-bctp tape and reel in dry p a ck bga124 8x8mm , 0.5mm pitch as3658c-bctp tape and reel in dry pa ck bga124 8x8mm , 0.5mm pitch as3658d-bctp tape and reel in dry p a ck bga124 8x8mm , 0.5mm pitch as3658e-bctp tape and reel in dry p a ck bga124 8x8mm , 0.5mm pitch AS3658E1-BCTP tape and reel in dry pa ck bga124 8x8mm , 0.5mm pitch as3658f-bctp tape and reel in dry p a ck bga124 8x8mm , 0.5mm pitch description: as3658x-bctp x: boot-rom version b: teperature range: z = -40oc to 85oc ct: pacakage: ctbga p:delivery form: tape and reel in dry pack as3658b power a nd audio management unit for portable devices, boot-rom version b as3658c power a nd audio management unit for portable devices, boot-rom version c as3658d power and audio management unit for portable devices, boot-rom version d as3658e power a nd audio management unit for portable devices, boot-rom version e as3658e1 power a nd audio management unit for portable devices, boot-rom version e1 as3658f power and audio management unit for portable devices, boot-rom version f ams ag technical content still valid www.austriamicrosystems.com revision 1v13 157 - 157 as3658 data sheet confidential - ordering information copyrights copyright ? 1997-201 0, austriamicrosystems ag, schloss premstaett en, 8141 unterpremstae tten, austria-europe. trademarks registered ?. all rights reserved. the mate rial herein may not be reproduced, adapted, merged, translated, stored, or used wit hout the prior written consent of the copyright owner. all products and companies mentioned are trademarks or reg istered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freed om of the described devices from patent infringement. austriamicrosystems ag reserves the right to change spec ifications and prices at an y time and without notice. therefore, prior to designing this pro duct into a system, it is necessary to check with austriam icrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environ mental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the m anufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is bel ieved to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to pe rsonal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to reci pient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag a-8141 schloss premstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors a nd representatives, please visit: http://www.austriamicrosystems.com/contact b ams ag technical content still valid |
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